Texas Instruments DS110DF1610FBE/NOPB

Overview

DS110DF1610FBE/NOPB from Texas Instruments is a 16-channel, multi-rate retimer IC for high-speed serial links operating from 8.5 to 11.3 Gbps per channel, featuring integrated CTLE, DFE, CDR, and 3-tap FIR transmit equalization. It delivers BER < 1×10⁻¹⁵ over lossy copper interconnects and backplanes with up to 4×4 analog cross point switching per quad, all powered by a single 2.5-V ±5% supply.

For engineers reviewing the DS110DF1610FBE/NOPB datasheet, DS110DF1610FBE/NOPB pinout, DS110DF1610FBE/NOPB application, or DS110DF1610FBE/NOPB equivalent, this device supports IEEE 1149.1/1149.6 JTAG, on-chip eye monitoring (EOM), PRBS generation/checking, and SMBus- or EEPROM-based configuration - critical for PCIe Gen4, SAS-3, and 10G/25G Ethernet retiming validation and production test.

Technical Context

The DS110DF1610FBE/NOPB implements independent per-channel adaptive signal conditioning: fully adaptive CTLE (6–38 dB boost, 3 bandwidth settings) and self-tuning DFE operate before CDR lock acquisition and remain active during operation. Its analog 4×4 cross point switches reside between CTLE and DFE stages, enabling non-blocking intra-quad routing without introducing digital latency or clock domain constraints.

Each channel includes AC-coupled CML inputs with on-chip 100-Ω termination, adjustable VOD (400–1200 mVpp), and precise jitter control: total output jitter ≤8.6 ps (10.3125 Gbps, PRBS-7, 1e⁻¹²), deterministic jitter ≤3.15 ps, and PLL bandwidth of 6.35–8.43 MHz across data rates. Reference clock support includes 25/125/312.5 MHz LVDS/LVCMOS inputs with ±100 ppm tolerance.

Key Specifications

Pinout & Package

DS110DF1610FBE/NOPB uses a 15-mm × 15-mm, 196-pin FCBGA package (ball pitch: 0.8 mm) with exposed thermal pad. Pin assignment follows JEDEC MO-271 standard; power/ground distribution supports low-noise high-speed operation across all 16 channels.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar retimer applications.

Compared with DS125DF1610 and DS150DF1610, the DS110DF1610FBE/NOPB provides optimal trade-off of power efficiency (210–368 mW/channel), jitter performance (≤8.6 ps), and 8.5–11.3 Gbps coverage - making it the preferred choice for cost-sensitive PCIe Gen4 and SAS-3 deployments where 12.5+ Gbps headroom is unnecessary.

Availability

DS110DF1610FBE/NOPB is available at Aetrix Electronics and suitable for PCIe Gen4 switch fabrics, SAS-3 storage backplanes, and 10G/25G Ethernet line cards requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for DS110DF1610FBE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions, with decades of expertise in signal integrity and SerDes technology.

The DS110DF1610FBE/NOPB belongs to TI's DS1xxDF1610 retimer family, engineered specifically for multi-gigabit serial link extension in data center, enterprise storage, and telecom infrastructure where adaptive equalization and diagnostic visibility are mission-critical.

FAQ

What data rates does the DS110DF1610FBE/NOPB support?

The DS110DF1610FBE/NOPB supports full-rate operation from 8.5 to 11.3 Gbps per channel, plus half-rate (4.25–5.65 Gbps), quarter-rate (2.125–2.825 Gbps), and eighth-rate (1.0625–1.4125 Gbps) modes. This multi-rate capability enables backward compatibility with legacy protocols like PCIe Gen3 and SAS-2 while supporting emerging 10G/25G Ethernet standards. All rates maintain BER < 1×10⁻¹⁵ under specified conditions.

Does the DS110DF1610FBE/NOPB require an external reference clock?

Yes, the DS110DF1610FBE/NOPB requires an external reference clock applied to REF_CLK_P/REF_CLK_N pins. It accepts 25 MHz, 125 MHz, or 312.5 MHz LVDS or single-ended LVCMOS signals with ±100 ppm tolerance. The reference clock accelerates CDR lock acquisition but is not strictly required for basic operation - the device can achieve lock using only the incoming data stream, albeit with longer acquisition time.

How many channels does the DS110DF1610FBE/NOPB have, and how are they grouped?

The DS110DF1610FBE/NOPB has 16 independent high-speed serial channels, organized into four quads of four channels each (e.g., Quad 0: RX_0A–RX_0D / TX_0A–TX_0D). Each quad contains a dedicated 4×4 analog cross point switch, allowing full non-blocking routing within the quad - such as mapping RX_0A to TX_3B - without affecting other quads or introducing digital latency.

Can the DS110DF1610FBE/NOPB be configured without a microcontroller?

Yes, the DS110DF1610FBE/NOPB supports autonomous configuration via external EEPROM connected to its SMBus interface. When EN_SMB is pulled high, the device acts as an SMBus master and loads configuration registers at power-up - eliminating dependency on host firmware. Configuration can also be performed dynamically via SMBus commands from an MCU or FPGA during runtime.

What diagnostic capabilities does the DS110DF1610FBE/NOPB provide?

The DS110DF1610FBE/NOPB integrates on-chip Eye Opening Monitor (EOM), PRBS pattern generator, and PRBS checker - enabling real-time link health assessment without external test equipment. It also provides input signal detection, CDR lock status flags, and interrupt reporting via INTERR_IO. These features allow full standalone BERT measurements and in-system debugging of high-speed serial links.