Analog Devices Inc./Maxim Integrated DS1123LE-100+
- Part No.:
- DS1123LE-100+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS1123LE-100+.pdf
- Description:
- IC DELAY LN 256TAP 255NS 16TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,469
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Product details
Overview
DS1123LE-100+ from Maxim Integrated is an 8-bit, 3.3V programmable delay line IC capable of full 0–360° clock phase shifting via 256 discrete 1ns delay steps (max 255ns), with on-chip reference delay for differential timing, and configurable as monostable vibrator or free-running oscillator. It serves in high-precision clock alignment for digital video projection systems.
For engineers reviewing the DS1123LE-100+ datasheet, DS1123LE-100+ pinout, DS1123LE-100+ application, or DS1123LE-100+ equivalent, key selection criteria include guaranteed monotonicity, ±4ns integral nonlinearity, 16-pin TSSOP package compatibility, and dual parallel/3-wire serial programming interface support.
Technical Context
The DS1123LE-100+ implements a 256-line decoder architecture with 255 unit delay cells, enabling delay adjustment from step-zero (16.5–22ns) up to 272ns relative to IN, or 255ns relative to REF. Its reference delay (18–22ns) is tightly matched to step-zero delay to enable sub-step relative timing.
It supports three functional modes: delay line (MS = 0), monostable vibrator (MS = 1, PWM output), and free-running oscillator (MS = 1 with OUT→IN feedback). Mode selection is hardware-controlled via MS pin, independent of programming interface.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay Step Size | 1ns typical; enables precise 0–255ns programmable delay increments in delay line mode. |
| Max Delay (vs REF) | 255ns; allows full-period clock phase shift up to 360° at ≤25MHz input frequency. |
| Integral Nonlinearity | ±4ns; deviation from ideal linear delay vs step count, measured relative to REF output. |
| Supply Voltage | +3.0V to +3.6V; single 3.3V rail operation with 16mA–30mA active current draw. |
| Programming Interface | Parallel (8-bit P0–P7) or 3-wire serial (CLK/D/Q); P/S pin selects mode at power-up. |
| Operating Temperature | 0°C to +70°C; specified performance across commercial temperature range. |
Pinout & Package
DS1123LE-100+ is housed in a 16-pin 150-mil thin shrink small outline package (TSSOP) with standard JEDEC MO-153 footprint and 0.65mm lead pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 IN | Signal Input | Primary input for delay line, monostable trigger, or oscillator feedback path. |
| 2 LE | Latch Enable | Active-high control for parallel data capture; low-to-high transition latches P0–P7 values. |
| 3 P0/Q | Data I/O | Parallel bit 0 input / serial data output; bidirectional in serial mode for daisy-chain readback. |
| 4 P1/CLK | Clock I/O | Parallel bit 1 input / serial clock input; drives shift register during serial programming. |
| 5 P2/D | Data I/O | Parallel bit 2 input / serial data input; accepts LSB-first 8-bit delay value in serial mode. |
| 9 REF/PWM | Reference or PWM Output | Provides matched reference delay (18–22ns) or monostable pulse-width modulated output when MS = 1. |
| 11 MS | Mode Select | Hardware-configured function selector: MS = 0 → delay line; MS = 1 → oscillator or PWM. |
| 14 P/S | Interface Select | Ground = parallel mode; VCC = 3-wire serial mode; determines programming interface at power-up. |
| 15 OUT/OUT | Delay Output | Inverting/non-inverting delay output; delta delay ≤2.5ns between normal and inverted paths. |
| 16 VCC | Power Supply | 3.3V supply input; requires local 0.01µF + 0.1µF ceramic decoupling per layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Full 360° Phase Shift | Enables complete clock cycle alignment by delaying up to one full period or more using 256-step resolution. |
| On-Chip Reference Delay | 18–22ns matched delay path (REF/PWM) eliminates step-zero offset, enabling true zero-relative differential timing. |
| Guaranteed Monotonicity | Ensures delay increases strictly with programmed step count-critical for jitter-sensitive clock recovery applications. |
| Dual Programming Interfaces | Parallel (microprocessor direct) and 3-wire serial (I/O-efficient cascading) allow flexible system integration without bus contention. |
| Triple Functional Modes | Single device supports delay line, monostable vibrator (5ns min pulse), and free-running oscillator (0.98–22MHz range). |
Applications
| Telecommunications Clock Alignment | Digital Video Projection Timing |
|---|---|
Use Scenario: Aligning multiple high-speed serial data lanes in backplane transceivers to compensate for trace-length skew. IC Role / Device Role / Timing Role: Programmable delay element synchronizing recovered clocks across SERDES channels. Use Value: Achieves sub-nanosecond inter-lane skew correction using 1ns step resolution and ±4ns INL. | Use Scenario: Precise pixel clock phase tuning in DLP or LCD projector timing controllers to eliminate image tearing. IC Role / Device Role / Timing Role: Adjustable clock delay generator feeding display controller PLL inputs. Use Value: Enables real-time 0–360° phase sweep via microprocessor-controlled parallel interface for optimal frame sync. |
| Signal Generator Calibration | Digital Test Equipment Triggering |
Use Scenario: Calibrating timebase accuracy in arbitrary waveform generators by injecting known delay offsets into reference paths. IC Role / Device Role / Timing Role: Traceable delay standard referenced to internal REF output for metrology-grade verification. Use Value: Leverages matched REF/OUT delay tracking over voltage/temperature to maintain <±0.75% relative delay tolerance. | Use Scenario: Generating precisely timed stimulus pulses for boundary-scan test patterns in ATE systems. IC Role / Device Role / Timing Role: Monostable vibrator producing 5–255ns programmable-width triggers synchronized to system clock. Use Value: Delivers deterministic pulse widths with no retriggering risk due to hardware-enforced monostable behavior. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1023S-100+ | 5V operation, same 8-bit architecture and 1ns step size, but lacks REF output and 3-wire serial interface. | Not suitable for 3.3V systems or differential timing applications requiring reference delay matching. | Select DS1023S-100+ only for legacy 5V designs where REF output and serial cascade are unnecessary. |
| LMK03806RGTT | Integrated PLL-based jitter cleaner with programmable delay; higher power, larger QFN package, and complex register map. | Targets ultra-low-jitter clock generation rather than simple tap-delay line functionality. | Choose LMK03806RGTT when system requires sub-ps jitter cleaning and integrated clock synthesis-not for basic delay insertion. |
Compared with DS1023S-100+, DS1123LE-100+ adds 3.3V compatibility, on-chip reference delay, and serial cascade capability; compared with LMK03806RGTT, it offers simpler configuration, lower cost, and deterministic nanosecond-scale delay without PLL lock time or loop filter design.
Availability
DS1123LE-100+ is available at Aetrix Electronics and suitable for telecommunications infrastructure, digital video projection, and automated test equipment requiring stable component supply with guaranteed long-term availability.
Supply support for DS1123LE-100+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in precision analog, mixed-signal, and power management ICs for industrial, communications, and computing markets.
The DS1123L product line delivers programmable nanosecond-resolution timing elements for clock alignment, signal conditioning, and waveform shaping in high-speed digital systems.
FAQ
What is the maximum achievable delay range for DS1123LE-100+ in delay line mode?
The DS1123LE-100+ provides a maximum delay of 272ns relative to the IN input, or 255ns relative to the REF output, corresponding to its 1ns step size and 256-step resolution. This enables full 360° phase shifting for input frequencies up to 25MHz, as confirmed in the AC Electrical Characteristics table for DS1123L-100.
How does the reference delay (REF/PWM pin) improve timing accuracy in DS1123LE-100+ applications?
The REF output on DS1123LE-100+ provides a 18–22ns delay path closely matched to the step-zero delay of the main OUT path. This allows users to measure delay relative to REF instead of IN, eliminating fixed offset errors and enabling true zero-relative differential timing critical for skew compensation and calibration tasks.
Can DS1123LE-100+ be used as a free-running oscillator, and what is its frequency range?
Yes, DS1123LE-100+ can operate as a free-running oscillator by setting MS = 1 and connecting OUT to IN. Its output frequency ranges from 0.98MHz (minimum, at max delay) to 22MHz (maximum, at step-zero delay), as specified in Table 2 of the datasheet for the DS1123L-100 speed grade.
What are the power supply requirements and decoupling recommendations for DS1123LE-100+?
DS1123LE-100+ requires a single 3.3V supply (VCC = +3.0V to +3.6V) and draws 16–30mA. Maxim specifies mandatory decoupling with both a 0.01µF and 0.1µF ceramic capacitor placed as close as possible to the VCC and GND pins to suppress high-frequency noise and ensure stable delay performance.
Is DS1123LE-100+ pin-compatible with other DS1123L variants such as DS1123LE-25+ or DS1123LE-200+?
Yes, all DS1123L speed variants-including DS1123LE-100+, DS1123LE-25+, and DS1123LE-200+-share identical 16-pin TSSOP packaging, pinout, and electrical interface. Only the internal delay cell characteristics differ; no PCB layout changes are required when substituting between speed grades.
DS1123LE-100+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Taps/Steps:
- 256
- Function:
- 1-Shot, Programmable
- Delay to 1st Tap:
- 16.5ns
- Tap Increment:
- 1 ns
- Available Total Delays:
- 255ns
- Number of Independent Delays:
- 1
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
DS1123LE-100+ FAQ
1.How can I place an order for DS1123LE-100+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1123LE-100+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1123LE-100+ reliable?
The price and inventory of DS1123LE-100+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1123LE-100+ is usually 5 days.
3.What payment methods are accepted for DS1123LE-100+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1123LE-100+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1123LE-100+?
DS1123LE-100+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1123LE-100+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1123LE-100+?
For technical support, including DS1123LE-100+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1123LE-100+ requirements.
6.How does Aetrix verify that DS1123LE-100+ is sourced from the original manufacturer or authorized distributors?
All DS1123LE-100+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1123LE-100+ meets industry standards.
7.What is the process for return or replacement of DS1123LE-100+?
All DS1123LE-100+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1123LE-100+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1123LE-100+ part is unused and in its original packaging.
Return procedure for DS1123LE-100+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1123LE-100+ Tags

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LTC6994CS6-1#TRMPBF
Analog Devices Inc.

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LTC6994CDCB-1#TRMPBF
Analog Devices Inc.

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LTC6994IS6-1#TRMPBF
Analog Devices Inc.

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LTC6994IS6-1#TRPBF
Analog Devices Inc.

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LTC6994IDCB-1#TRMPBF
Analog Devices Inc.

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LTC6994IS6-2#TRMPBF
Analog Devices Inc.

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LTC6994HS6-1#TRPBF
Analog Devices Inc.

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LTC6994HS6-1#TRMPBF
Analog Devices Inc.

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LTC6994HS6-2#TRMPBF
Analog Devices Inc.

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LTC6994HDCB-2#TRMPBF
Analog Devices Inc.

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LTC6994HDCB-1#TRMPBF
Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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