Analog Devices Inc./Maxim Integrated DS1123LE-50+
- Part No.:
- DS1123LE-50+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS1123LE-50+.pdf
- Description:
- IC DEL LN 256TAP 127.5NS 16TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,551
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1123LE-50+ from Maxim Integrated is an 8-bit programmable timing element operating at 3.3V, functioning as a precision delay line, monostable vibrator, or free-running oscillator. It delivers 0.5ns step resolution across 256 steps (0–127.5ns max delay), supports parallel and 3-wire serial programming, and enables full 0°–360° clock phase shifting in telecom and test equipment.
For engineers reviewing the DS1123LE-50+ datasheet, DS1123LE-50+ pinout, DS1123LE-50+ application, or DS1123LE-50+ equivalent, key selection considerations include step size accuracy, reference-delay-referenced delay tolerance (±0.75%), monotonicity guarantee, 16-pin TSSOP package compatibility, and dual-mode operation (MS = 0 for delay line, MS = 1 for PWM/oscillator).
Technical Context
The DS1123LE-50+ implements an 8-bit latch-driven 255-stage delay cell array with on-chip reference delay (tREF = 18–22ns) matched to step-zero delay (tD0 = 16.5–22ns), enabling sub-step-zero relative delays. Its architecture supports both absolute delay (IN→OUT) and differential delay (REF→OUT), with integral nonlinearity bounded at ±2ns over full scale.
It features dual programming interfaces: parallel (P0–P7, LE, P/S = GND) for microprocessor control and 3-wire serial (CLK/P1, D/P2, Q/P0) for cascaded multi-device systems. Mode selection via MS pin determines functional behavior-delay line (MS = 0), or monostable/PWM/oscillator (MS = 1) with OUT-to-IN feedback.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay Step Size | 0.5ns typical - enables precise 256-step delay tuning from 0 to 127.5ns with monotonic response. |
| Reference Delay (tREF) | 18–22ns - closely tracks step-zero delay to support zero/negative relative delays vs. REF output. |
| Delay Tolerance (vs. REF) | ±0.75% at VCC = 3.3V, TA = +25°C - ensures predictable delay shift across voltage variations. |
| Integral Nonlinearity | ±2ns - deviation from ideal straight-line delay response, critical for phase-critical clock alignment. |
| Supply Voltage | +3.0V to +3.6V - single 3.3V rail operation compatible with modern low-voltage digital systems. |
| Operating Temperature | 0°C to +70°C - commercial-grade range suitable for telecom infrastructure and benchtop test gear. |
| Power Supply Current | 16–30mA - active/standby ICC enables thermal-aware system power budgeting. |
Pinout & Package
DS1123LE-50+ is housed in a 16-pin TSSOP (150-mil width) package with exposed pad not electrically connected. Pin functions are validated per Maxim's official pin configuration diagram and functional description.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 IN | Signal Input / PWM Trigger | Primary input for delay line mode; rising edge triggers monostable/PWM when MS = 1. |
| 2 LE | Latch Enable | High = transparent latch (parallel mode); low = latched value active; controls serial data capture timing. |
| 3 P0/Q | Parallel Data Bit 0 / Serial Output | LSB of parallel load; serial data output for daisy-chaining multiple devices. |
| 4 P1/CLK | Parallel Data Bit 1 / Serial Clock | Second bit in parallel mode; clocks serial data into 8-bit register on rising edge. |
| 5 P2/D | Parallel Data Bit 2 / Serial Input | Third bit in parallel mode; serial data input for programming cascade chain. |
| 9 REF/PWM | Reference Output / PWM Output | Fixed-delay reference signal (≈tREF); becomes PWM output in monostable mode (MS = 1). |
| 11 MS | Mode Select | Low = delay line; high = monostable vibrator or oscillator (with OUT→IN feedback). |
| 14 P/S | Parallel/Serial Select | GND = parallel interface enabled; VCC = 3-wire serial interface enabled. |
| 15 OUT/OUT | Delay Output / Inverted Output | Programmable delay output; inverted version available via internal logic selection. |
| 16 VCC | Power Supply | +3.3V supply pin; requires local 0.01µF + 0.1µF ceramic decoupling per layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| 0.5ns step resolution with 256 settings | Enables fine-grained phase alignment in clock recovery and jitter cleanup circuits without external PLLs. |
| On-chip reference delay (18–22ns) | Allows differential delay measurement against REF, supporting sub-step-zero timing offsets for skew compensation. |
| Guaranteed monotonic delay response | Ensures deterministic timing behavior across all 256 steps-critical for closed-loop calibration and real-time adjustment. |
| Dual programming interfaces | Parallel mode supports fast microprocessor updates; 3-wire serial enables scalable multi-delay systems with minimal I/O. |
| Configurable functional modes | Single device serves delay line, monostable vibrator (5ns min pulse), or oscillator (0.98–22MHz range) via MS pin. |
Applications
| Telecom Clock Phase Alignment | Digital Test Signal Conditioning |
|---|---|
|
Use Scenario: Aligning transmit/receive clock edges in SFP+ or CPRI-based fronthaul links to minimize setup/hold violations. IC Role / Device Role / Timing Role: Programmable delay line referenced to REF output to nullify board-level skew between SERDES lanes. Use Value: Achieves sub-1ns relative delay resolution (±0.75% tolerance) across temperature, eliminating need for custom PCB trace tuning. |
Use Scenario: Generating precisely timed stimulus pulses for boundary-scan or JTAG-based IC validation. IC Role / Device Role / Timing Role: Monostable vibrator triggered by pattern generator, producing 5–127.5ns calibrated pulses with fixed rise/fall times. Use Value: Replaces discrete RC timers with guaranteed monotonicity and no drift-enabling repeatable pass/fail thresholds in ATE. |
| Digital Video Pixel Clock Shaping | RF Signal Generator Calibration |
|
Use Scenario: Adjusting HDMI or DisplayPort pixel clock phase to match panel driver timing requirements across varying cable lengths. IC Role / Device Role / Timing Role: Free-running oscillator mode (MS = 1 + OUT→IN) generating stable 1.9–22MHz clocks with 1ns step granularity. Use Value: Delivers jitter-free, digitally tunable clock sources without crystal replacements or complex PLL loop design. |
Use Scenario: Introducing calibrated time offsets between RF LO and baseband sampling clocks in vector signal analyzers. IC Role / Device Role / Timing Role: Dual-output delay line providing synchronized but offset-triggered signals to mixer and ADC paths. Use Value: Enables direct measurement of group delay and phase response using REF/OUT differential timing-no external time-interval analyzer needed. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable timing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1023S-50+ | 5V operation, 0.5ns step, same 256-step range but higher supply current (45mA typ) and no REF output. | Limited to legacy 5V systems; lacks differential delay capability and monotonicity guarantee. | Select DS1123LE-50+ for 3.3V designs requiring REF-referenced delay or sub-step-zero offsets. |
| LMK03806RHAT | Integrated PLL + 8-channel programmable delay, 100fs RMS jitter, SPI interface only, 3.3V supply. | Higher complexity and cost; targets ultra-low-jitter clock generation-not pure delay line use cases. | Choose DS1123LE-50+ when simplicity, low latency (<500ns parallel load), and monostable/PWM modes are prioritized over jitter performance. |
Compared with DS1023S-50+, DS1123LE-50+ reduces supply voltage and adds REF output for differential timing; compared with LMK03806RHAT, it offers lower latency, simpler interface options, and dedicated monostable functionality-making it optimal for deterministic, low-overhead delay tasks in test and telecom hardware.
Availability
DS1123LE-50+ is available at Aetrix Electronics and suitable for telecommunications infrastructure, digital test equipment, digital video projection, and signal generator applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for DS1123LE-50+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, communications, and computing markets, with emphasis on high-reliability timing, power, and interface solutions.
The DS1123L family was developed to provide field-programmable, low-jitter delay elements for clock phase alignment, test signal conditioning, and programmable pulse generation-targeting applications where analog delay lines lack resolution and PLLs add complexity.
FAQ
What is the maximum delay achievable with DS1123LE-50+ in delay line mode?
The DS1123LE-50+ achieves a maximum delay of 127.5ns with respect to the REF output when programmed to step 255. This value is derived from its 0.5ns step size and 256-step range. The absolute delay from IN to OUT at step 255 is up to 144ns, but REF-referenced delay is the more stable and specified metric due to tighter voltage/temperature tracking between REF and OUT outputs.
How does DS1123LE-50+ support differential delay measurements?
DS1123LE-50+ supports differential delay measurements via its dedicated REF/PWM pin, which provides a fixed ~20ns delay closely matched to the step-zero delay (tD0). By measuring delay between REF and OUT instead of IN and OUT, designers achieve sub-step-zero resolution and reduced sensitivity to supply/temperature variation-enabling precise skew compensation in high-speed interfaces.
Can DS1123LE-50+ operate as a free-running oscillator, and what frequency range is supported?
Yes, DS1123LE-50+ can operate as a free-running oscillator by setting MS = 1 and connecting OUT to IN. In this configuration, oscillation period equals twice the programmed delay, yielding frequencies from 0.98MHz (max delay) to 22MHz (min delay). The actual range depends on the selected step value and is documented in Table 2 of the datasheet.
Is DS1123LE-50+ pin-compatible with other DS1123L speed grades?
Yes, DS1123LE-50+ is pin-compatible with DS1123LE-25+, DS1123LE-100+, and DS1123LE-200+. All share identical 16-pin TSSOP packaging, pinout, and interface logic. Only the delay step size and maximum delay differ-allowing drop-in replacement during design iteration or performance tuning without PCB changes.
What is the minimum pulse width DS1123LE-50+ can generate in monostable mode?
In monostable vibrator mode (MS = 1), DS1123LE-50+ guarantees a minimum usable output pulse width of 5ns. This is limited by the output driver's physical slew rate and is specified under standard test conditions (VCC = 3.3V, TA = +25°C). Narrower pulses may be observed but risk degraded logic levels or missing transitions.
DS1123LE-50+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Taps/Steps:
- 256
- Function:
- 1-Shot, Programmable
- Delay to 1st Tap:
- 16.5ns
- Tap Increment:
- 500 ps
- Available Total Delays:
- 127.5ns
- Number of Independent Delays:
- 1
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
DS1123LE-50+ FAQ
1.How can I place an order for DS1123LE-50+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1123LE-50+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1123LE-50+ reliable?
The price and inventory of DS1123LE-50+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1123LE-50+ is usually 5 days.
3.What payment methods are accepted for DS1123LE-50+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1123LE-50+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1123LE-50+?
DS1123LE-50+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1123LE-50+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1123LE-50+?
For technical support, including DS1123LE-50+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1123LE-50+ requirements.
6.How does Aetrix verify that DS1123LE-50+ is sourced from the original manufacturer or authorized distributors?
All DS1123LE-50+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1123LE-50+ meets industry standards.
7.What is the process for return or replacement of DS1123LE-50+?
All DS1123LE-50+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1123LE-50+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1123LE-50+ part is unused and in its original packaging.
Return procedure for DS1123LE-50+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1123LE-50+ Tags

-
LTC6994CS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994CDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRPBF
Analog Devices Inc.

-
LTC6994IDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-1#TRMPBF
Analog Devices Inc.

-
DS1124U-25+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

