Analog Devices Inc./Maxim Integrated DS1135LU-12+
- Part No.:
- DS1135LU-12+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
DS1135LU-12+.pdf
- Description:
- IC DELAY LINE 12NS 8UMAX
- Quantity:
- Payment:

- Shipping:

Inventory:4,662
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Product details
Overview
DS1135LU-12+ from Maxim Integrated is a 3V, triple-output all-silicon delay line delivering precise 12ns propagation delay (tPLH/tPHL) on each of three independent buffered outputs, with ±1.0ns initial tolerance and ±3.0ns tolerance over -40°C to +85°C; used for clock/data alignment in high-speed digital systems including FPGA I/O timing and memory interface deskew.
For engineers reviewing the DS1135LU-12+ datasheet, DS1135LU-12+ pinout, DS1135LU-12+ application, or DS1135LU-12+ equivalent, key selection criteria include guaranteed edge-to-edge delay symmetry, 3V operation with 2.7V–3.6V supply range, industrial temperature support, and SO-8 (150-mil) package compatibility with vapor-phase and IR reflow processes.
Technical Context
The DS1135LU-12+ implements three identical, fully buffered delay paths in a single monolithic silicon circuit, each preserving input signal symmetry via matched leading- and trailing-edge delay accuracy. It operates without external components and requires no configuration or clock input.
Its logic-level compatible inputs accept 0.8V/2.0V thresholds across full supply range, while outputs drive 74F04-equivalent loads with 2.0–2.5ns rise/fall times and stable 12ns delay under varying voltage (±3.0ns over 2.7V–3.6V) and temperature (-40°C to +85°C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 12ns (tPLH/tPHL), matched across all three outputs for simultaneous signal deskew |
| Initial delay tolerance | ±1.0ns at +25°C, 3.3V - enables tight setup/hold margin control without calibration |
| Temp/voltage tolerance | ±3.0ns over -40°C to +85°C and 2.7V–3.6V - ensures deterministic timing in industrial environments |
| Supply voltage | 2.7V–3.6V - compatible with modern 3V logic families and low-power system rails |
| Output rise/fall time | 2.0–2.5ns - supports clean transitions into 15pF loads at high frequencies |
| Power-up time | 1ms - allows immediate use after power stabilization, no initialization sequence required |
Pinout & Package
DS1135LU-12+ is housed in an 8-pin SOIC (150-mil) package, RoHS-compliant and rated for vapor-phase and IR reflow soldering.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Independent logic inputs | Accept TTL/CMOS-compatible signals; each drives one dedicated delay path |
| OUT1, OUT2, OUT3 | Buffered delay outputs | Provide 12ns-delayed, low-skew copies of respective inputs; drive 74F04-equivalent loads |
| VCC | Positive supply | Single 3V rail (2.7V–3.6V); powers all three delay paths and buffers |
| GND | Ground reference | Common return for inputs, outputs, and internal circuitry; critical for delay stability |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon construction | Eliminates aging, drift, and mechanical failure modes inherent in analog or LC-based delay solutions |
| Leading/trailing edge precision | Maintains input waveform symmetry - essential for duty-cycle-sensitive interfaces like DDR strobes |
| Three independent buffered delays | Enables parallel deskew of multiple signals (e.g., DQS/DQ groups) without cross-talk or loading interaction |
| Industrial temperature range | Guaranteed 12ns delay performance from -40°C to +85°C - suitable for embedded control and telecom infrastructure |
Applications
| Memory Interface Deskew | FPGA I/O Timing Alignment |
|---|---|
Use Scenario: Aligning DQS and DQ signals in DDR2/DDR3 memory subsystems to meet strict setup/hold windows. IC Role / Device Role / Timing Role: DS1135LU-12+ provides matched 12ns delay on DQS path to compensate for PCB trace length mismatch relative to DQ lines. Use Value: Enables reliable data capture at >400MT/s without custom layout tuning or active feedback loops. | Use Scenario: Synchronizing multiple clock domains between FPGA fabric and external peripherals (e.g., ADCs, DACs). IC Role / Device Role / Timing Role: DS1135LU-12+ delivers deterministic, low-jitter delay on clock enable or sample strobe lines to align sampling edges across channels. Use Value: Reduces inter-channel skew to <3ns, improving effective ENOB in multi-channel acquisition systems. |
| High-Speed Logic Glue | Test Equipment Signal Conditioning |
Use Scenario: Compensating propagation delay mismatches in backplane or mezzanine board interconnects. IC Role / Device Role / Timing Role: DS1135LU-12+ inserts calibrated delay into control or status lines to realign handshake timing across distributed logic blocks. Use Value: Eliminates need for discrete RC networks or programmable logic-based delay elements, reducing BOM count and layout complexity. | Use Scenario: Calibrating trigger and sampling path delays in automated test equipment (ATE) channel cards. IC Role / Device Role / Timing Role: DS1135LU-12+ serves as a stable, repeatable delay reference for channel-to-channel skew verification and compensation. Use Value: Provides traceable, temperature-stable 12ns offset without requiring recalibration during thermal cycling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135LZ-12+ | Same die, identical delay specs and pinout; differs only in tape-and-reel packaging (Z = SO, U = tube) | No functional difference; U-tube preferred for prototyping, Z-tape for production | Select DS1135LU-12+ for low-volume evaluation or manual assembly; DS1135LZ-12+ for SMT line integration |
| DS1035Z-12+ | 5V-only operation (4.5V–5.5V), same 12ns delay but higher ICC (15mA vs. 10mA) and wider temp tolerance (±5ns over -40°C to +85°C) | Not suitable for 3V systems; usable only where legacy 5V logic coexists | Choose DS1135LU-12+ for new 3V designs; DS1035Z-12+ only if maintaining 5V infrastructure |
Compared with DS1135LZ-12+, DS1135LU-12+ offers identical timing performance in tube packaging for flexibility in small-batch builds; versus DS1035Z-12+, it enables lower-power, 3V-native system integration with tighter delay tolerance and reduced supply sensitivity.
Availability
DS1135LU-12+ is available at Aetrix Electronics and suitable for memory interface deskew, FPGA timing alignment, and high-speed logic glue applications requiring stable component supply and guaranteed industrial-temperature performance.
Supply support for DS1135LU-12+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, communications, and computing applications.
The DS1135L series was developed to replace aging discrete delay solutions with a robust, all-silicon alternative for deterministic signal alignment in 3V digital systems.
FAQ
What is the operating voltage range for DS1135LU-12+?
The DS1135LU-12+ operates from 2.7V to 3.6V, with typical performance characterized at 3.3V. Its input thresholds (VIH ≥ 2.0V, VIL ≤ 0.8V) and output drive capability remain fully specified across this range, making DS1135LU-12+ suitable for battery-powered or regulated 3V systems where supply variation occurs.
Does DS1135LU-12+ require external components or configuration?
No, DS1135LU-12+ is a fully self-contained delay line requiring only VCC and GND connections. It has no pins for configuration, trim, or bypass; all three 12ns delay paths are active and independent upon power-up, with no initialization sequence or external timing reference needed for DS1135LU-12+ operation.
How does DS1135LU-12+ ensure matching between leading and trailing edge delays?
DS1135LU-12+ uses matched internal circuitry for rising- and falling-edge propagation paths, guaranteeing tPLH and tPHL both equal 12ns ±1.0ns initially and ±3.0ns over temperature/voltage. This symmetry preserves input duty cycle - a critical feature confirmed in the datasheet's "Leading and Trailing Edge Precision" specification for DS1135LU-12+.
Is DS1135LU-12+ pin-compatible with DS1033-series devices?
Yes, DS1135LU-12+ is a recommended replacement for DS1033-series delay lines and shares the same 8-pin SOIC (150-mil) footprint and pin assignment (IN1–IN3, OUT1–OUT3, VCC, GND). However, DS1135LU-12+ operates at 3V only, whereas DS1033 is 5V-only - direct substitution requires verifying supply voltage compatibility before using DS1135LU-12+.
What is the maximum load capacitance supported by DS1135LU-12+ outputs?
DS1135LU-12+ outputs are specified to drive a 15pF capacitive load with 2.0–2.5ns rise/fall times and stable 12ns delay. Driving heavier loads increases transition time and may degrade delay accuracy; for loads exceeding 15pF, buffer amplification or layout optimization is recommended to maintain DS1135LU-12+ timing integrity.
DS1135LU-12+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 12ns
- Tap Increment:
- -
- Available Total Delays:
- 12ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-uMAX/uSOP
DS1135LU-12+ FAQ
1.How can I place an order for DS1135LU-12+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LU-12+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LU-12+ reliable?
The price and inventory of DS1135LU-12+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LU-12+ is usually 5 days.
3.What payment methods are accepted for DS1135LU-12+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LU-12+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LU-12+?
DS1135LU-12+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LU-12+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LU-12+?
For technical support, including DS1135LU-12+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LU-12+ requirements.
6.How does Aetrix verify that DS1135LU-12+ is sourced from the original manufacturer or authorized distributors?
All DS1135LU-12+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LU-12+ meets industry standards.
7.What is the process for return or replacement of DS1135LU-12+?
All DS1135LU-12+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LU-12+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LU-12+ part is unused and in its original packaging.
Return procedure for DS1135LU-12+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LU-12+ Tags

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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