Analog Devices Inc./Maxim Integrated DS1135LU-15
- Part No.:
- DS1135LU-15
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
DS1135LU-15.pdf
- Description:
- IC DELAY LINE 15NS 8UMAX
- Quantity:
- Payment:

- Shipping:

Inventory:3,482
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1135LU-15 from Maxim Integrated is a 3V, 3-in-1 high-speed silicon delay line delivering precise 15 ns propagation delays (tPLH/tPHL) across all three independent buffered outputs, with ±1.0 ns initial tolerance and ±2.5 ns tolerance over -40°C to +85°C, used in high-speed digital timing alignment for FPGA clock deskew and logic synchronization.
For engineers reviewing the DS1135LU-15 datasheet, DS1135LU-15 pinout, DS1135LU-15 application, or DS1135LU-15 equivalent, key selection factors include guaranteed leading/trailing edge symmetry, 2.7–3.6 V supply operation, sub-3 ns output rise/fall time, and SO-8 (150-mil) package compatibility with industrial temperature requirements.
Technical Context
The DS1135LU-15 implements three fully independent, logic-buffered delay paths in a single monolithic silicon IC, each with matched tPLH and tPHL values of 15 ns under nominal conditions (25°C, 3.3 V). Its all-silicon architecture eliminates quartz-based drift and enables stable performance across voltage (2.7–3.6 V) and temperature (-40°C to +85°C).
It preserves input signal symmetry via precision edge alignment-critical for maintaining duty cycle integrity in high-speed clock distribution. The device features TTL/CMOS-compatible inputs and outputs, supports 100% of delay-value minimum pulse width, and achieves <3 ns output transition times with 15 pF load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 15 ns (tPLH/tPHL), matched across all three channels for synchronous signal alignment |
| Initial delay tolerance | ±1.0 ns at 25°C/3.3 V - ensures tight timing budget margin in first-pass designs |
| Tolerance over temp/volt | ±2.5 ns (-40°C to +85°C, 2.7–3.6 V) - guarantees deterministic latency in harsh environments |
| Supply voltage range | 2.7 V to 3.6 V - compatible with modern 3V logic families and low-power systems |
| Output rise/fall time | 2.0–2.5 ns (15 pF load) - supports >300 MHz signal edges without distortion |
| Operating temperature | -40°C to +85°C - qualified for industrial-grade embedded and communications equipment |
Pinout & Package
DS1135LU-15 is housed in an 8-pin SOIC package (150-mil width, package code S8+2, outline 21-0041), RoHS-compliant and compatible with vapor-phase and IR reflow soldering processes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Digital input signals | Three independent TTL/CMOS-compatible inputs accepting 0.0–3.0 V pulses; each drives one delay path |
| OUT1, OUT2, OUT3 | Buffered delayed outputs | Three logic-buffered outputs delivering identical 15 ns delay with matched edge timing |
| VCC | Positive supply | +3V supply pin (2.7–3.6 V); powers all three delay paths and buffers |
| GND | Ground reference | Common return for inputs, outputs, and internal circuitry; required for noise immunity and timing stability |
Key Features
| Feature | Design Value |
|---|---|
| Precision leading/trailing edge delay | Identical tPLH and tPHL (15 ns) preserves input duty cycle and minimizes jitter accumulation in cascaded logic |
| All-silicon construction | Eliminates quartz aging, shock sensitivity, and frequency drift-ideal for long-life industrial deployments |
| Three independent buffered delays | Enables parallel timing correction of multiple signal paths without cross-talk or loading interaction |
| Industrial temperature support | Guaranteed 15 ns delay performance across -40°C to +85°C-no derating or recalibration needed |
Applications
| High-Speed FPGA Clock Deskew | Logic-Level Signal Synchronization |
|---|---|
Use Scenario: Aligning multiple clock domains between FPGA I/O banks to meet setup/hold timing across PCB traces of unequal length. IC Role / Device Role / Timing Role: DS1135LU-15 provides deterministic, matched 15 ns delays on three independent clock paths to compensate for inter-bank skew. Use Value: Eliminates need for programmable delay blocks or external PLLs-reduces FPGA resource usage and simplifies timing closure. | Use Scenario: Synchronizing asynchronous control signals (e.g., reset, enable, latch strobes) across multi-chip digital subsystems. IC Role / Device Role / Timing Role: DS1135LU-15 delivers identical, edge-accurate delays to three critical control lines, ensuring simultaneous assertion/deassertion. Use Value: Prevents metastability and race conditions in state machines by guaranteeing sub-3 ns inter-output skew. |
| Industrial Bus Timing Calibration | Test Equipment Pulse Delay Generation |
Use Scenario: Compensating for propagation delay mismatches in RS-485 or CAN FD transceiver timing paths within motor drive controllers. IC Role / Device Role / Timing Role: DS1135LU-15 inserts calibrated 15 ns delay into transmit/receive enable paths to align driver output with bus arbitration windows. Use Value: Ensures compliance with ISO 11898-2 timing margins without custom PCB trace tuning. | Use Scenario: Generating precisely timed stimulus pulses for automated test equipment (ATE) channel calibration and jitter analysis. IC Role / Device Role / Timing Role: DS1135LU-15 acts as a fixed, low-jitter delay element in pulse generator front-ends, feeding synchronized triggers to DUT inputs. Use Value: Provides repeatable, temperature-stable delay (±2.5 ns) without software-controlled DACs or analog delay lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135LZ-15+ | Same die, identical 15 ns delay specs, but uses standard SO-8 (150-mil) with lead-free plating; DS1135LU-15 is Maxim's legacy marking variant | No functional difference; both qualified for industrial temp and 3V operation | Select DS1135LZ-15+ for new designs requiring documented RoHS compliance and current Maxim ordering codes |
| MAX9601EUA+ | Single-channel, 15 ns delay; no multi-output capability; higher ICC (15 mA vs. 10 mA); same SO-8 package | Suitable only when only one delay path is needed; lacks parallel 3-output synchronization | Choose MAX9601EUA+ if board space or BOM count must be minimized and multi-path alignment is unnecessary |
Compared with DS1135LU-15, DS1135LZ-15+ offers identical timing performance with updated packaging documentation, while MAX9601EUA+ trades triple-output synchronization for lower component count in single-path applications-making DS1135LU-15 optimal for deterministic multi-signal deskew where inter-channel skew must remain below 300 ps.
Availability
DS1135LU-15 is available at Aetrix Electronics and suitable for high-speed FPGA interfacing, industrial bus timing calibration, and automated test equipment requiring stable component supply with guaranteed industrial temperature operation and precise fixed delay.
Supply support for DS1135LU-15 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, communications, and computing applications.
The DS1135L series was developed as a low-power, 3V-compatible replacement for legacy DS1033 delay lines-targeting high-reliability, fixed-latency signal alignment in space-constrained digital systems.
FAQ
What is the exact delay value and tolerance of DS1135LU-15?
The DS1135LU-15 delivers a nominal 15 ns propagation delay (tPLH and tPHL) on each of its three outputs. Initial tolerance is ±1.0 ns at 25°C and 3.3 V. Over the full industrial temperature range (-40°C to +85°C) and supply voltage (2.7–3.6 V), delay tolerance is ±2.5 ns-guaranteed by Maxim's characterization data.
Is DS1135LU-15 pin-compatible with DS1033 or other legacy delay lines?
No, DS1135LU-15 is not pin-compatible with DS1033. It uses an 8-pin SOIC package with three inputs and three outputs plus VCC and GND, whereas DS1033 is a 14-pin DIP with different pinout and timing architecture. DS1135LU-15 is explicitly positioned as a functional replacement-not a drop-in substitute-and requires PCB layout revision.
Does DS1135LU-15 support both rising and falling edge delays equally?
Yes, DS1135LU-15 provides identical 15 ns delay for both rising (tPLH) and falling (tPHL) edges on all three outputs. This leading/trailing edge precision preserves input signal symmetry and duty cycle integrity-critical for clock distribution and high-speed logic interfacing.
What is the maximum operating frequency supported by DS1135LU-15?
DS1135LU-15 does not specify a maximum frequency directly, but its AC characteristics require input pulse width (tWI) to be ≥100% of the delay value (i.e., ≥15 ns). With 2.5 ns typical output rise/fall time and 15 pF load, it reliably supports input periods down to ~50 ns-enabling use with signals up to ~20 MHz fundamental frequency and harmonics beyond 300 MHz.
Can DS1135LU-15 operate from a 2.5V supply?
No, DS1135LU-15 is specified only for 2.7 V to 3.6 V operation. At 2.5 V, timing parameters-including delay accuracy and output drive strength-are not guaranteed. The DC electrical characteristics table explicitly defines VCC min as 2.7 V, and operation below this violates the device's validated operating conditions.
DS1135LU-15 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 15ns
- Tap Increment:
- -
- Available Total Delays:
- 15ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-uMAX/uSOP
DS1135LU-15 FAQ
1.How can I place an order for DS1135LU-15 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LU-15 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LU-15 reliable?
The price and inventory of DS1135LU-15 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LU-15 is usually 5 days.
3.What payment methods are accepted for DS1135LU-15?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LU-15 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LU-15?
DS1135LU-15 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LU-15 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LU-15?
For technical support, including DS1135LU-15 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LU-15 requirements.
6.How does Aetrix verify that DS1135LU-15 is sourced from the original manufacturer or authorized distributors?
All DS1135LU-15 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LU-15 meets industry standards.
7.What is the process for return or replacement of DS1135LU-15?
All DS1135LU-15 units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LU-15, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LU-15 part is unused and in its original packaging.
Return procedure for DS1135LU-15:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LU-15 Tags

-
LTC6994CS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994CDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRPBF
Analog Devices Inc.

-
LTC6994IDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-1#TRMPBF
Analog Devices Inc.

-
DS1124U-25+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

