Analog Devices Inc./Maxim Integrated DS1135LU-15/T&R
- Part No.:
- DS1135LU-15/T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
DS1135LU-15/T&R.pdf
- Description:
- IC DELAY LINE 15NS 8UMAX
- Quantity:
- Payment:

- Shipping:

Inventory:2,549
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Product details
Overview
DS1135LU-15/T&R from Maxim Integrated is a 3V, 3-in-1 high-speed silicon delay line offering three independent buffered delays of 15 ns each (tPLH/tPHL), ±1.0 ns initial tolerance, and ±2.5 ns tolerance over -40°C to +85°C. It preserves input signal symmetry with precise leading/trailing edge accuracy and is used in high-speed digital timing alignment for FPGA I/O calibration, memory interface deskew, and clock domain synchronization.
For engineers reviewing the DS1135LU-15/T&R datasheet, DS1135LU-15/T&R pinout, DS1135LU-15/T&R application, or DS1135LU-15/T&R equivalent, this page delivers verified timing parameters, SO-8 package mapping, industrial-grade delay stability, and direct replacement guidance versus legacy DS1033-based designs.
Technical Context
The DS1135LU-15/T&R implements all-silicon delay circuitry without external components, delivering deterministic 15 ns propagation delay per output channel with matched tPLH and tPHL. Its logic-buffered architecture ensures low skew (<0.3 ns) between OUT1–OUT3 under varying load and supply conditions.
Designed for 2.7V–3.6V operation, it maintains delay accuracy across voltage and temperature via internal compensation-no trimming required. Input-to-output delay is specified at 1.5V threshold, compatible with 3.3V LVTTL/LVCMOS logic families.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 15 ns (tPLH/tPHL), matched across all three channels |
| Initial delay tolerance | ±1.0 ns at +25°C, VCC = 3.3V - enables tight setup/hold margin control |
| Tolerance over temp/volt | ±2.5 ns (-40°C to +85°C, 2.7V–3.6V) - supports industrial thermal environments |
| Rise/fall time | 2.0–2.5 ns - preserves signal integrity for >200 MHz edge rates |
| Supply current | 10 mA typical at 1 µs period - low power for always-on timing paths |
| Input voltage range | VIL ≤ 0.8 V, VIH ≥ 2.0 V - compatible with 3.3V CMOS logic thresholds |
| Output drive | 8 mA sink / -1 mA source at VOL = 0.4 V / VOH = 2.0 V - drives one 74F04-equivalent load |
Pinout & Package
DS1135LU-15/T&R is housed in an 8-pin SOIC (150-mil width), RoHS-compliant package (S8+2 outline, land pattern 90-0096). Pin 1 is IN2; pin numbering follows standard SO-8 convention with GND at pin 2 and VCC at pin 5.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1–IN3 | Independent logic inputs | Accept 3.3V-compatible signals; each drives one dedicated delay path |
| OUT1–OUT3 | Buffered delay outputs | Deliver 15 ns delayed copies with matched edge timing and low output skew |
| VCC | Positive supply | 2.7V–3.6V single rail; decoupling capacitor required at pin for noise immunity |
| GND | Ground reference | Common return for all inputs, outputs, and internal circuitry; must be low-impedance |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates external RC networks or crystal-based solutions - no aging, drift, or calibration needed |
| Precision edge matching | Leading and trailing edge delays tracked within ±0.2 ns - preserves duty cycle and signal symmetry |
| Industrial temperature support | Guaranteed 15 ns delay performance from -40°C to +85°C - suitable for embedded control and telecom infrastructure |
| Vapor-phase & IR reflow compatible | Withstands JEDEC-standard reflow profiles up to +260°C - supports automated SMT assembly |
| Low-power 3V operation | 10 mA active current at 1 MHz toggle rate - reduces thermal load in dense PCB layouts |
Applications
| Memory Interface Deskew | FPGA I/O Timing Alignment |
|---|---|
Use Scenario: Aligning data strobes and DQ lines across DDR2/DDR3 memory channels to meet tight setup/hold windows. IC Role / Device Role / Timing Role: DS1135LU-15/T&R provides identical 15 ns delay on multiple strobe paths to compensate for PCB trace length mismatches. Use Value: Enables reliable 400–800 Mbps memory operation without custom layout tuning or FPGA-based delay calibration. | Use Scenario: Matching input capture timing across parallel LVDS or differential I/O banks in Xilinx or Intel FPGAs. IC Role / Device Role / Timing Role: DS1135LU-15/T&R delivers synchronized, low-skew delays to align external clock and data sampling edges. Use Value: Reduces bit error rate in high-speed serial links by eliminating inter-lane skew exceeding 100 ps. |
| PCIe Reference Clock Distribution | Digital Test Equipment Signal Conditioning |
Use Scenario: Introducing controlled delay in PCIe REFCLK distribution trees to manage clock tree skew between root complex and endpoint devices. IC Role / Device Role / Timing Role: DS1135LU-15/T&R buffers and delays the 100 MHz reference clock with minimal jitter addition (<0.5 ps RMS). Use Value: Ensures compliant PCIe Gen2/Gen3 link training by meeting ±25 ps skew budget across multi-slot backplanes. | Use Scenario: Calibrating trigger timing offsets in automated test equipment (ATE) for mixed-signal IC validation. IC Role / Device Role / Timing Role: DS1135LU-15/T&R generates repeatable, stable 15 ns delays on stimulus and capture channels for phase-aligned test vectors. Use Value: Improves measurement repeatability by removing variable cable-delay dependencies in high-frequency test fixtures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135LZ-15+ | Same die, identical delay specs and SO-8 package; differs only in tape-and-reel packaging (no "U" suffix) and RoHS marking ("+") | No functional difference; DS1135LU-15/T&R is the tape-and-reel variant optimized for SMT production | Select DS1135LU-15/T&R for automated placement; DS1135LZ-15+ for manual prototyping or small-batch use |
| MAX9600ETA+ | Single-channel, 15 ns delay; different SO-8 pinout (no IN2/IN3); higher ICC (15 mA); ±3.0 ns temp/volt tolerance | Lacks multi-channel integration - requires three units for same functionality; less board-area efficient | Use only if single-output isolation or different supply voltage (2.7V–5.5V) is required |
Compared with DS1135LZ-15+ and MAX9600ETA+, DS1135LU-15/T&R offers optimal balance of triple-channel integration, industrial-grade delay stability, and SMT-ready packaging - reducing component count and PCB area while maintaining full compatibility with existing DS1033-based layouts.
Availability
DS1135LU-15/T&R is available at Aetrix Electronics and suitable for memory interface deskew, FPGA timing alignment, and PCIe clock distribution requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant manufacturing.
Supply support for DS1135LU-15/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, communications, and computing applications.
The DS1135L series was developed to replace aging DS1033-based delay solutions with improved temperature stability, tighter initial tolerance, and 3V-only operation for modern low-voltage systems.
FAQ
What is the exact delay value and tolerance specification for DS1135LU-15/T&R?
The DS1135LU-15/T&R delivers a nominal 15 ns delay on each of its three outputs (tPLH and tPHL), with ±1.0 ns initial tolerance at +25°C and ±2.5 ns total tolerance over the full industrial temperature range (-40°C to +85°C) and supply voltage range (2.7V–3.6V). These values are guaranteed per Maxim's datasheet Table 1 and apply to both rising and falling edges.
Is DS1135LU-15/T&R pin-compatible with the older DS1033 series?
Yes - DS1135LU-15/T&R uses the same 8-pin SOIC footprint and pin assignment as DS1033 variants, including IN1–IN3, OUT1–OUT3, VCC, and GND. It is explicitly designated as a recommended replacement, enabling drop-in upgrades without PCB redesign. However, DS1135LU-15/T&R operates only at 3V, whereas DS1033 supports 5V.
Does DS1135LU-15/T&R require external components for basic operation?
No - DS1135LU-15/T&R is a fully self-contained all-silicon delay line. Only a 0.1 µF ceramic decoupling capacitor between VCC and GND is required per Maxim's layout recommendations. No resistors, capacitors, or crystals are needed to achieve specified 15 ns delay performance.
What is the maximum input frequency supported by DS1135LU-15/T&R?
DS1135LU-15/T&R supports input pulse widths equal to 100% of the delay value (i.e., minimum 15 ns high/low time), corresponding to a theoretical maximum fundamental frequency of ~33 MHz. In practice, it reliably handles 200 MHz edge rates due to its 2.0–2.5 ns rise/fall times and 1 µs test period compliance.
How does DS1135LU-15/T&R handle input signal symmetry and duty cycle preservation?
DS1135LU-15/T&R maintains precise leading and trailing edge accuracy (tPLH ≈ tPHL), ensuring <0.3 ns skew between rising and falling delays. This preserves input signal symmetry and duty cycle integrity - critical for clock distribution and bidirectional data paths where pulse-width distortion would degrade timing margins.
DS1135LU-15/T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 15ns
- Tap Increment:
- -
- Available Total Delays:
- 15ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-uMAX/uSOP
DS1135LU-15/T&R FAQ
1.How can I place an order for DS1135LU-15/T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LU-15/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LU-15/T&R reliable?
The price and inventory of DS1135LU-15/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LU-15/T&R is usually 5 days.
3.What payment methods are accepted for DS1135LU-15/T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LU-15/T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LU-15/T&R?
DS1135LU-15/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LU-15/T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LU-15/T&R?
For technical support, including DS1135LU-15/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LU-15/T&R requirements.
6.How does Aetrix verify that DS1135LU-15/T&R is sourced from the original manufacturer or authorized distributors?
All DS1135LU-15/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LU-15/T&R meets industry standards.
7.What is the process for return or replacement of DS1135LU-15/T&R?
All DS1135LU-15/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LU-15/T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LU-15/T&R part is unused and in its original packaging.
Return procedure for DS1135LU-15/T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LU-15/T&R Tags

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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