Analog Devices Inc./Maxim Integrated DS1135LU-25+T&R
- Part No.:
- DS1135LU-25+T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
DS1135LU-25+T&R.pdf
- Description:
- IC DELAY LINE 25NS 8UMAX
- Quantity:
- Payment:

- Shipping:

Inventory:3,227
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Product details
Overview
DS1135LU-25+T&R from Maxim Integrated is a 3V, 3-in-1 high-speed silicon delay line delivering precise 25 ns propagation delay on all three independent buffered outputs (tPLH/tPHL = 25/25/25 ns), with ±1.5 ns initial tolerance and ±5.0 ns total tolerance over -40°C to +85°C. It preserves input signal symmetry via leading/trailing edge accuracy and targets timing-critical logic synchronization in industrial control and test equipment.
For engineers reviewing the DS1135LU-25+T&R datasheet, DS1135LU-25+T&R pinout, DS1135LU-25+T&R application, or DS1135LU-25+T&R equivalent, key selection criteria include guaranteed 25 ns delay stability across voltage (2.7–3.6 V) and temperature, 8-pin SOIC (150-mil) package compatibility, and replacement suitability for legacy DS1033-based designs requiring improved edge fidelity and low-power 3V operation.
Technical Context
The DS1135LU-25+T&R implements three fully independent, logic-buffered delay paths within a single monolithic silicon die-no external components required. Each path delivers matched 25 ns propagation delay with identical tPLH and tPHL values, ensuring deterministic skew control between outputs.
It operates strictly at 3V (2.7–3.6 V), uses CMOS-compatible input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V), and guarantees sub-nanosecond edge precision: output rise/fall times are 2.0–2.5 ns into 15 pF load, with power-up stabilization in ≤1 ms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 25 ns (tPLH/tPHL), matched across all three outputs for synchronized timing paths |
| Initial delay tolerance | ±1.5 ns at +25°C, VCC = 3.3 V - enables tight setup/hold margin planning |
| Temp/voltage tolerance | ±5.0 ns over -40°C to +85°C and 2.7–3.6 V - ensures robustness in industrial environments |
| Supply voltage | 2.7 V to 3.6 V - compatible with modern 3V logic families without level-shifting |
| Output rise/fall time | 2.0–2.5 ns into 15 pF - supports high-speed digital interfaces up to ~200 MHz |
| Active supply current | 10 mA max at VCC = 3.6 V, 1 µs period - low static power for battery-sensitive systems |
| Input capacitance | 10 pF typical - minimizes loading on preceding driver stage |
Pinout & Package
DS1135LU-25+T&R is housed in an 8-pin SOIC package (150-mil width, outline 21-0041), RoHS-compliant (indicated by '+' suffix), vapor-phase and IR-reflow solderable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Dedicated input signals for each delay channel | CMOS-compatible inputs accepting 0–3.3 V logic; no internal termination required |
| OUT1, OUT2, OUT3 | Buffered delay outputs with matched 25 ns propagation | Drive 74F04-equivalent loads; 2.0–2.5 ns edge rates support clean signal integrity |
| VCC | +3V supply rail | Must be decoupled locally; operates only within 2.7–3.6 V range |
| GND | Ground reference | Common return for all inputs, outputs, and supply; critical for delay stability |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates aging, drift, and environmental sensitivity inherent in RC or analog delay solutions |
| Precision leading/trailing edge matching | Maintains input waveform symmetry - essential for clock distribution and data strobing |
| Three independent buffered delays | Enables parallel timing paths without cross-talk or shared loading effects |
| Industrial temperature range support | Guaranteed 25 ns delay performance from -40°C to +85°C - suitable for harsh environments |
| Tape-and-reel packaging | Optimized for automated SMT assembly; 'T&R' suffix confirms reel format availability |
Applications
| Logic Timing Alignment | Test Equipment Signal Conditioning |
|---|---|
Use Scenario: Aligning asynchronous control signals (e.g., reset, enable, latch) across multiple FPGA I/O banks to meet setup/hold timing windows. IC Role / Device Role / Timing Role: Precision delay element providing deterministic 25 ns offset per channel to resolve inter-bank skew. Use Value: Eliminates need for PCB trace-length tuning; maintains signal integrity with matched tPLH/tPHL and <2.5 ns edge rates. | Use Scenario: Introducing calibrated delays in ATE stimulus channels to synchronize pattern generation with DUT response sampling. IC Role / Device Role / Timing Role: Stable, repeatable 25 ns delay block used in multi-channel timing calibration fixtures. Use Value: ±5.0 ns worst-case tolerance over temperature ensures measurement repeatability across environmental chambers. |
| Industrial PLC Input Synchronization | Digital Communication Skew Compensation |
Use Scenario: Synchronizing fast-response sensor inputs (e.g., encoder quadrature edges) before feeding into real-time motion controllers. IC Role / Device Role / Timing Role: Low-jitter delay buffer preserving edge fidelity for deterministic interrupt timing. Use Value: Leading/trailing edge accuracy prevents duty-cycle distortion; 10 mA ICC enables direct integration into 3V PLC I/O modules. | Use Scenario: Compensating for fixed interconnect skew between parallel data lanes in LVDS or CMOS bus interfaces. IC Role / Device Role / Timing Role: Matched 25 ns delay applied to selected lanes to realign sampled data at receiver. Use Value: Three independent outputs allow per-lane adjustment without external buffering; SOIC footprint simplifies board layout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar delay-line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135LZ-25+ | Same die, identical 25 ns delay specs, but packaged in standard SO (S8+2); DS1135LU-25+T&R specifies tape-and-reel delivery format | No functional difference; U-suffix denotes tape-and-reel packaging per Maxim ordering convention | Select DS1135LU-25+T&R for SMT production; DS1135LZ-25+ for sample or manual assembly |
| MAX9602ESE+ | Single-output, 25 ns delay; higher ICC (15 mA), wider VCC range (2.7–5.5 V); different SO-8 pinout | Lacks triple-output capability; requires three devices for equivalent functionality | Choose only if mixed-voltage system design demands 5V compatibility or single-channel isolation is preferred |
Compared with DS1135LZ-25+, DS1135LU-25+T&R offers identical electrical performance but optimized logistics for volume SMT use; versus MAX9602ESE+, it provides integrated triple-delay functionality in one SO-8 package, reducing board area and component count by 67%.
Availability
DS1135LU-25+T&R is available at Aetrix Electronics and suitable for industrial automation, test instrumentation, and programmable logic controller (PLC) designs requiring stable component supply, precise 25 ns timing alignment, and RoHS-compliant 3V silicon delay solutions.
Supply support for DS1135LU-25+T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, communications, and computing applications.
The DS1135L series was developed to replace aging discrete or hybrid delay solutions with monolithic, temperature-stable silicon alternatives-specifically targeting 3V logic synchronization where edge fidelity and multi-channel matching are critical.
FAQ
What is the exact delay value and tolerance of DS1135LU-25+T&R?
The DS1135LU-25+T&R delivers precisely 25 ns propagation delay on each of its three outputs (tPLH/tPHL = 25/25/25 ns). Initial tolerance is ±1.5 ns at +25°C and 3.3 V; total tolerance over -40°C to +85°C and 2.7–3.6 V is ±5.0 ns. These values are guaranteed per Maxim's datasheet Table 1 and apply identically to all three channels.
Is DS1135LU-25+T&R pin-compatible with DS1033?
DS1135LU-25+T&R is specified as a recommended replacement for DS1033, but it is not pin-compatible: DS1033 uses a 14-pin DIP or SO package with different pin assignments and delay architecture. DS1135LU-25+T&R uses an 8-pin SOIC (150-mil) with dedicated IN1–IN3/OUT1–OUT3 pins. PCB redesign is required for migration.
Does DS1135LU-25+T&R support 5V operation?
No. DS1135LU-25+T&R is strictly a 3V device with absolute maximum VCC of +6.0 V but operational specification limited to 2.7–3.6 V. Applying 5V violates DC electrical characteristics and may damage the device. For 5V systems, consider discrete delay solutions or level-shifted interface designs.
What does the 'U' in DS1135LU-25+T&R signify?
The 'U' suffix in DS1135LU-25+T&R indicates tape-and-reel packaging per Maxim's ordering nomenclature. It denotes the same silicon and electrical specifications as DS1135LZ-25+, but supplied in automated assembly-ready format. The '+' confirms RoHS compliance; 'T&R' explicitly confirms tape-and-reel delivery.
Can DS1135LU-25+T&R drive standard TTL or CMOS loads?
Yes. DS1135LU-25+T&R outputs are designed to drive one 74F04-equivalent load (≈20 pF, 1 mA sink/source), with guaranteed VOL ≤ 0.4 V and VOH ≥ 2.0 V under specified conditions. Its 2.0–2.5 ns rise/fall times and 10 mA drive strength make it compatible with 74LVC, 74ALVC, and most 3V CMOS families without external buffering.
DS1135LU-25+T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 25ns
- Tap Increment:
- -
- Available Total Delays:
- 25ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-uMAX/uSOP
DS1135LU-25+T&R FAQ
1.How can I place an order for DS1135LU-25+T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LU-25+T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LU-25+T&R reliable?
The price and inventory of DS1135LU-25+T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LU-25+T&R is usually 5 days.
3.What payment methods are accepted for DS1135LU-25+T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LU-25+T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LU-25+T&R?
DS1135LU-25+T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LU-25+T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LU-25+T&R?
For technical support, including DS1135LU-25+T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LU-25+T&R requirements.
6.How does Aetrix verify that DS1135LU-25+T&R is sourced from the original manufacturer or authorized distributors?
All DS1135LU-25+T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LU-25+T&R meets industry standards.
7.What is the process for return or replacement of DS1135LU-25+T&R?
All DS1135LU-25+T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LU-25+T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LU-25+T&R part is unused and in its original packaging.
Return procedure for DS1135LU-25+T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LU-25+T&R Tags

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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