Analog Devices Inc./Maxim Integrated DS1135LZ-10+
- Part No.:
- DS1135LZ-10+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135LZ-10+.pdf
- Description:
- IC DELAY LINE 10NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,605
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Product details
Overview
DS1135LZ-10+ from Maxim Integrated is a 3V, triple-output all-silicon delay line delivering precise 10 ns ±1.0 ns (25°C) leading/trailing edge delays across IN1→OUT1, IN2→OUT2, and IN3→OUT3. It operates over -40°C to +85°C with ±3.0 ns total tolerance, supports 2.7–3.6 V supply, and features <2.5 ns output rise/fall time for high-speed digital timing alignment in FPGA clock deskew and logic synchronization.
For engineers reviewing the DS1135LZ-10+ datasheet, DS1135LZ-10+ pinout, DS1135LZ-10+ application, or DS1135LZ-10+ equivalent, this page delivers verified delay accuracy, SO-8 package mapping, industrial temperature validation, and direct replacement context versus legacy DS1033-series devices.
Technical Context
The DS1135LZ-10+ implements three independent buffered delay paths using all-silicon circuitry-no external capacitors or trimming required. Each path maintains matched tPLH/tPHL ≤ ±1.0 ns initial tolerance and preserves input signal symmetry via edge-aligned propagation.
It operates strictly at 3V nominal (2.7–3.6 V range), draws ≤10 mA active current, and achieves sub-2.5 ns output transitions into 15 pF loads-enabling reliable use in 100 MHz+ digital systems where jitter-sensitive timing alignment is critical.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 10 ns ±1.0 ns (25°C); ensures deterministic skew control across three parallel signals |
| Supply voltage | 2.7 V to 3.6 V; compatible with modern 3V logic families without level-shifting |
| Temp range | -40°C to +85°C; validated for industrial-grade embedded and telecom equipment |
| Rise/fall time | ≤2.5 ns (15 pF load); supports clean edge integrity in fast CMOS interfaces |
| Input capacitance | 10 pF typical; minimizes loading on upstream drivers like FPGA I/O or clock buffers |
| Power-up time | 1 ms; guarantees stable delay output within one millisecond of VCC stabilization |
Pinout & Package
DS1135LZ-10+ is housed in an 8-pin SOIC (150-mil width) package, RoHS-compliant, vapor-phase and IR-reflow solderable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Dedicated delay input channels | Accept independent TTL/CMOS-compatible logic inputs; each drives one buffered delay path |
| OUT1, OUT2, OUT3 | Corresponding delayed outputs | Deliver 10 ns delayed copies with matched edge fidelity; drive 74F04-equivalent loads |
| VCC | Positive supply | Single 3V rail powers all three delay paths; no separate analog/digital supplies needed |
| GND | Ground reference | Common return for all inputs, outputs, and internal circuitry; requires low-impedance PCB connection |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates capacitor drift and temperature hysteresis-delivers stable delay over life and thermal cycling |
| Precision leading & trailing edge matching | Maintains input duty cycle integrity; essential for clock deskew and pulse-width-critical applications |
| Three independent buffered outputs | Enables simultaneous delay of multiple control or clock signals without cross-talk or loading interaction |
| Industrial temperature operation | Validated performance from -40°C to +85°C-suitable for base station, motor control, and industrial PLC designs |
Applications
| FPGA Clock Deskew | Digital Logic Synchronization |
|---|---|
Use Scenario: Aligning multiple clock domains across large FPGA fabric to meet setup/hold timing. IC Role / Device Role / Timing Role: DS1135LZ-10+ provides matched 10 ns delays on three independent clock paths to compensate for trace-length skew. Use Value: Enables deterministic inter-clock phase alignment without custom PCB length tuning or PLL-based solutions. | Use Scenario: Synchronizing enable signals across distributed logic blocks in high-speed data acquisition systems. IC Role / Device Role / Timing Role: DS1135LZ-10+ delays three asynchronous control lines to align with a master sampling strobe. Use Value: Eliminates metastability risk by guaranteeing setup time compliance across all downstream latches. |
| Telecom Line Card Timing | Industrial Motor Control PWM Alignment |
Use Scenario: Compensating for propagation delay mismatches between transmit/receive clock paths in T1/E1 interface modules. IC Role / Device Role / Timing Role: DS1135LZ-10+ applies identical 10 ns delay to three reference clocks feeding serializer/deserializer ICs. Use Value: Reduces bit-error rate by ensuring deterministic clock-to-data alignment across multi-channel PHY layers. | Use Scenario: Aligning gate-drive timing across three-phase inverter legs to minimize shoot-through risk. IC Role / Device Role / Timing Role: DS1135LZ-10+ delays individual PWM outputs from a microcontroller to match power device switching latency. Use Value: Improves inverter efficiency and reliability by enabling precise dead-time insertion without firmware overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-output silicon delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1033Z-10+ | Slower 3V version (tR/tF ≤ 4 ns); wider initial delay tolerance (±2.5 ns); same SO-8 footprint | Lower-frequency logic systems (<50 MHz); less demanding skew budgets | Select DS1033Z-10+ only if cost sensitivity outweighs need for sub-2.5 ns edges and tighter delay matching |
| MAX9992ETE+ | Single-output, programmable 0–30 ns delay (100 ps steps); 3.3V operation; 16-pin TQFN | Applications requiring fine-grained, dynamic delay adjustment per channel | Choose MAX9992ETE+ when per-path delay tuning or reconfiguration during operation is required |
Compared with DS1033Z-10+, DS1135LZ-10+ delivers faster edges and tighter delay matching for high-speed systems; versus MAX9992ETE+, it offers fixed triple-output simplicity at lower BOM count and cost-but lacks programmability.
Availability
DS1135LZ-10+ is available at Aetrix Electronics and suitable for FPGA clock deskew, industrial motor control PWM alignment, and telecom line card timing requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for DS1135LZ-10+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, communications, and computing applications.
The DS1135L series targets high-reliability digital timing alignment-specifically replacing aging discrete or crystal-based delay solutions with robust, temperature-stable all-silicon alternatives in space-constrained SO-8 packages.
FAQ
What is the guaranteed delay accuracy of DS1135LZ-10+ over its full operating temperature range?
The DS1135LZ-10+ guarantees ±3.0 ns delay variation across -40°C to +85°C, measured as total deviation from nominal 10 ns at 25°C. This includes both initial tolerance (±1.0 ns) and additional drift due to temperature and supply voltage changes within 2.7–3.6 V.
Does DS1135LZ-10+ require external components for operation?
No, DS1135LZ-10+ is a fully self-contained delay line. It needs only a 3V supply (2.7–3.6 V), ground, and input signals-no external capacitors, resistors, or trimming components are required. Its all-silicon architecture eliminates dependency on passive elements.
Can DS1135LZ-10+ be used with 5V logic inputs?
No. DS1135LZ-10+ accepts inputs up to VCC + 0.5 V (max 4.1 V at 3.6 V supply). Direct 5V logic inputs exceed absolute maximum ratings and may damage the device. Level-shifting to ≤3.6 V is mandatory for compatibility.
Is DS1135LZ-10+ pin-compatible with DS1033Z-10+?
Yes-DS1135LZ-10+ and DS1033Z-10+ share identical 8-pin SOIC (150-mil) footprints and pin assignments (IN1–IN3, OUT1–OUT3, VCC, GND). No PCB layout change is needed when upgrading from DS1033Z-10+ to DS1135LZ-10+.
What is the maximum input frequency supported by DS1135LZ-10+?
DS1135LZ-10+ supports input pulses with minimum width equal to 100% of the delay value (i.e., ≥10 ns), corresponding to a theoretical maximum fundamental frequency of ~50 MHz. Practical use is validated up to 100 MHz systems when driven with clean, fast-edged signals meeting specified rise/fall time limits.
DS1135LZ-10+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 10ns
- Tap Increment:
- -
- Available Total Delays:
- 10ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135LZ-10+ FAQ
1.How can I place an order for DS1135LZ-10+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LZ-10+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LZ-10+ reliable?
The price and inventory of DS1135LZ-10+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LZ-10+ is usually 5 days.
3.What payment methods are accepted for DS1135LZ-10+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LZ-10+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LZ-10+?
DS1135LZ-10+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LZ-10+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LZ-10+?
For technical support, including DS1135LZ-10+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LZ-10+ requirements.
6.How does Aetrix verify that DS1135LZ-10+ is sourced from the original manufacturer or authorized distributors?
All DS1135LZ-10+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LZ-10+ meets industry standards.
7.What is the process for return or replacement of DS1135LZ-10+?
All DS1135LZ-10+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LZ-10+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LZ-10+ part is unused and in its original packaging.
Return procedure for DS1135LZ-10+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LZ-10+ Tags

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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