Analog Devices Inc./Maxim Integrated DS1135LZ-12+
- Part No.:
- DS1135LZ-12+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135LZ-12+.pdf
- Description:
- IC DELAY LINE 12NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,694
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1135LZ-12+ from Maxim Integrated is a 3V, 3-in-1 high-speed silicon delay line with three independent buffered outputs, each delivering precisely matched 12ns propagation delay (tPLH/tPHL), ±1.0ns initial tolerance, and ±3.0ns tolerance over -40°C to +85°C. It operates across 2.7V–3.6V, consumes ≤10mA active current, and preserves input signal symmetry via leading/trailing edge accuracy - used in clock skew management and digital timing alignment circuits.
For engineers reviewing the DS1135LZ-12+ datasheet, DS1135LZ-12+ pinout, DS1135LZ-12+ application, or DS1135LZ-12+ equivalent, key selection criteria include guaranteed 12ns delay matching across all three outputs, industrial temperature support, SO-8 (150-mil) package compatibility, and replacement suitability for legacy DS1033-based timing designs.
Technical Context
The DS1135LZ-12+ implements an all-silicon delay architecture with three independent logic-buffered delay paths, each with identical tPLH and tPHL values. Its design ensures sub-nanosecond edge alignment fidelity and maintains output symmetry under voltage variation (2.7V–3.6V) and full industrial temperature range (-40°C to +85°C).
No internal PLL or feedback loop is present; delay is fixed and passive-silicon-based. Power-up time is specified at 1ms, and output rise/fall times are ≤2.5ns into 15pF load - enabling use in high-speed digital systems requiring deterministic, low-jitter signal re-timing without clock regeneration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 12ns (tPLH/tPHL), matched across all three outputs for skew-critical timing alignment |
| Initial delay tolerance | ±1.0ns at +25°C/3.3V - enables precise system-level timing budgeting at power-on |
| Temp/voltage tolerance | ±3.0ns over -40°C to +85°C and 2.7V–3.6V - guarantees stable delay in harsh environments |
| Supply voltage range | 2.7V–3.6V - compatible with modern 3V logic families and low-power embedded systems |
| Active supply current | ≤10mA at 3.6V/1µs period - supports power-constrained board-level integration |
| Output rise/fall time | ≤2.5ns into 15pF - ensures clean transitions for 50MHz+ digital interfaces |
| Power-up time | 1ms - defines minimum reset-to-valid-output latency in cold-start applications |
Pinout & Package
DS1135LZ-12+ is housed in an 8-pin SOIC package (150-mil width, outline 21-0041), RoHS-compliant, vapor-phase and IR-reflow solderable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Dedicated input signals for each delay path | Accept TTL/CMOS-compatible logic inputs; no internal termination required |
| OUT1, OUT2, OUT3 | Buffered delay outputs with matched propagation | Drive one 74F04-equivalent load; 15pF test condition reflects typical FPGA/CPLD interface |
| VCC | +3V supply rail | Must be decoupled locally; supports 2.7V–3.6V operation with monotonic delay behavior |
| GND | Signal and power ground reference | Shared return for all inputs/outputs; critical for maintaining inter-channel delay match |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates quartz or analog RC dependencies - delivers inherent reliability and zero aging drift |
| Precision leading/trailing edge matching | Maintains input waveform symmetry (duty cycle preservation) across all three outputs |
| Three independent buffered delays | Enables parallel timing adjustment of multiple signal paths without cross-talk or loading interaction |
| Industrial temperature support | Validated operation from -40°C to +85°C - suitable for automotive control modules and industrial PLCs |
| Lead(Pb)-free/RoHS-compliant packaging | SO-8 (S8+2) footprint compatible with standard 150-mil land patterns and automated assembly |
Applications
| High-Speed Digital Test Equipment | Industrial PLC Timing Modules |
|---|---|
Use Scenario: Aligning trigger and sampling clocks in automated test equipment to eliminate setup/hold violations. IC Role / Device Role / Timing Role: Provides deterministic, matched 12ns delay across three synchronous data channels for phase calibration. Use Value: Enables sub-nanosecond channel-to-channel skew correction without external calibration firmware. | Use Scenario: Synchronizing I/O scan cycles and interrupt response timing in programmable logic controllers. IC Role / Device Role / Timing Role: Delays sensor input strobes and actuator enable signals to coordinate multi-stage control sequences. Use Value: Guarantees consistent 12ns delay across temperature and supply variations - eliminating recalibration during field deployment. |
| Medical Imaging Data Acquisition | Automotive ADAS Sensor Fusion |
Use Scenario: Time-aligning parallel ADC sample clocks in ultrasound beamforming front-ends. IC Role / Device Role / Timing Role: Buffers and delays reference clocks to compensate for PCB trace length mismatches between ADCs. Use Value: Preserves input signal symmetry and duty cycle - critical for maintaining SNR in high-resolution imaging. | Use Scenario: Matching time-of-flight signal paths from radar, lidar, and camera sensors in fusion processors. IC Role / Device Role / Timing Role: Introduces calibrated, temperature-stable delay to equalize propagation latency across heterogeneous sensor interfaces. Use Value: Reduces timing uncertainty to ±3.0ns over full automotive temperature range - improving fusion algorithm accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-in-1 fixed-delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1033Z-12+ | Slower 3V version (max 10MHz input); ±2.5ns temp/voltage tolerance; same SO-8 package | Limited to lower-frequency digital systems; less stable over temperature than DS1135LZ-12+ | Select when cost sensitivity outweighs need for high-speed pulse fidelity and tight delay stability |
| MAX9602ETA+ | Single-channel, 12ns delay; 3.3V-only supply; 6-pin SOT23 package; higher drive strength (±24mA) | Not pin-compatible; requires three devices for triple-delay function; better suited for driving heavy loads | Select when board space allows discrete implementation and higher output current is required |
Compared with DS1033Z-12+ and MAX9602ETA+, the DS1135LZ-12+ uniquely integrates three matched 12ns delays in one SO-8 package with superior temperature stability (±3.0ns vs ±2.5ns) and faster edge handling - making it optimal for compact, high-reliability multi-channel timing alignment.
Availability
DS1135LZ-12+ is available at Aetrix Electronics and suitable for high-speed digital test equipment, industrial PLC timing modules, medical imaging data acquisition, and automotive ADAS sensor fusion requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for DS1135LZ-12+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing solutions for industrial, medical, and communications applications.
The DS1135L series belongs to Maxim's fixed-delay line product line, engineered specifically for deterministic, low-skew signal re-timing in multi-channel digital systems where quartz-based or programmable alternatives introduce jitter or complexity.
FAQ
What is the guaranteed delay matching between OUT1, OUT2, and OUT3 on the DS1135LZ-12+?
The DS1135LZ-12+ guarantees identical 12ns propagation delay (tPLH/tPHL) across all three outputs, with ±1.0ns initial tolerance at +25°C/3.3V and ±3.0ns matching over -40°C to +85°C and 2.7V–3.6V. This ensures sub-nanosecond inter-channel skew in real-world operating conditions - critical for synchronized multi-path timing applications.
Does the DS1135LZ-12+ require external termination or biasing for proper operation?
No, the DS1135LZ-12+ does not require external termination or biasing. Inputs (IN1–IN3) accept standard TTL/CMOS logic levels, and outputs (OUT1–OUT3) are internally buffered to drive one 74F04-equivalent load (15pF). Local VCC decoupling is recommended, but no pull-ups, pull-downs, or series resistors are needed for nominal operation per the datasheet test conditions.
Can the DS1135LZ-12+ operate reliably at 2.7V supply voltage?
Yes, the DS1135LZ-12+ is fully specified and tested from 2.7V to 3.6V. At 2.7V, delay remains within ±3.0ns of nominal across -40°C to +85°C, and output drive capability meets 8mA sink/1mA source requirements into 15pF. This makes DS1135LZ-12+ suitable for battery-powered or low-voltage industrial systems where supply headroom is constrained.
Is the DS1135LZ-12+ pin-compatible with the DS1033Z-12+?
Yes, the DS1135LZ-12+ is pin-compatible with the DS1033Z-12+ - both use the same 8-pin SOIC (150-mil) package with identical pin assignments (IN1–IN3, OUT1–OUT3, VCC, GND). However, DS1135LZ-12+ offers improved speed, tighter delay tolerance, and enhanced temperature stability, allowing direct drop-in replacement in most existing DS1033Z-12+ designs without layout changes.
What is the maximum input frequency supported by the DS1135LZ-12+?
The DS1135LZ-12+ supports input pulses with period ≥2× delay value (i.e., ≥24ns minimum period), corresponding to a maximum fundamental frequency of ~41.7MHz. Input pulse width must be ≥100% of delay (≥12ns), and rise/fall times must be ≤3.0ns (20%–80%). These constraints ensure accurate delay measurement and output fidelity per the device's AC characterization methodology.
DS1135LZ-12+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 12ns
- Tap Increment:
- -
- Available Total Delays:
- 12ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135LZ-12+ FAQ
1.How can I place an order for DS1135LZ-12+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LZ-12+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LZ-12+ reliable?
The price and inventory of DS1135LZ-12+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LZ-12+ is usually 5 days.
3.What payment methods are accepted for DS1135LZ-12+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LZ-12+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LZ-12+?
DS1135LZ-12+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LZ-12+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LZ-12+?
For technical support, including DS1135LZ-12+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LZ-12+ requirements.
6.How does Aetrix verify that DS1135LZ-12+ is sourced from the original manufacturer or authorized distributors?
All DS1135LZ-12+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LZ-12+ meets industry standards.
7.What is the process for return or replacement of DS1135LZ-12+?
All DS1135LZ-12+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LZ-12+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LZ-12+ part is unused and in its original packaging.
Return procedure for DS1135LZ-12+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LZ-12+ Tags

-
LTC6994CS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994CDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRPBF
Analog Devices Inc.

-
LTC6994IDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-1#TRMPBF
Analog Devices Inc.

-
DS1124U-25+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
