Analog Devices Inc./Maxim Integrated DS1135LZ-15+
- Part No.:
- DS1135LZ-15+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135LZ-15+.pdf
- Description:
- IC DELAY LINE 15NS 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1135LZ-15+ from Maxim Integrated is a 3V, 8-pin SO (150-mil) all-silicon 3-in-1 high-speed delay line delivering three independent buffered delays of precisely 15 ns each (tPLH/tPHL), with ±1.0 ns initial tolerance and ±4.0 ns total tolerance over -40°C to +85°C. It preserves input signal symmetry via leading/trailing edge precision and supports industrial-grade timing in clock distribution, FPGA interface synchronization, and digital test equipment.
For engineers reviewing the DS1135LZ-15+ datasheet, DS1135LZ-15+ pinout, DS1135LZ-15+ application, or DS1135LZ-15+ equivalent, this page delivers verified timing accuracy, package mapping to SOIC-8, thermal/voltage stability data, and direct alternatives for delay-line replacement in high-reliability digital systems.
Technical Context
The DS1135LZ-15+ implements three independent logic-buffered delay paths in a single monolithic silicon structure, eliminating external RC networks and drift-prone analog delay elements. Each path guarantees matched 15 ns propagation delay (tPLH/tPHL) with sub-nanosecond edge alignment across temperature and supply voltage (2.7 V to 3.6 V).
Its architecture ensures simultaneous leading- and trailing-edge accuracy-critical for maintaining duty cycle integrity in clock fanout and data strobe applications. The device operates without external components and requires no configuration, functioning as a fixed, deterministic delay element upon power-up within 1 ms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 15 ns (tPLH/tPHL), matched across all three outputs |
| Initial delay tolerance | ±1.0 ns at +25°C, VCC = 3.3 V - enables precise setup/hold margin control |
| Tolerance over temp/volt | ±4.0 ns (-40°C to +85°C, 2.7–3.6 V) - ensures stable timing in industrial environments |
| Supply voltage range | 2.7 V to 3.6 V - compatible with modern 3V logic families and low-power systems |
| Output rise/fall time | 2.0–2.5 ns - supports >300 MHz signal edges without distortion |
| Power-up time | 1 ms - guarantees deterministic delay behavior after power stabilization |
| Input capacitance | 10 pF - minimizes loading on upstream drivers and preserves signal integrity |
Pinout & Package
DS1135LZ-15+ is housed in an 8-pin SOIC package (150-mil width), RoHS-compliant, vapor-phase and IR-reflow solderable. Pin 1 is IN2 (left-bottom corner when notch faces up); pinout follows standard SOIC numbering.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1–IN3 | Independent logic inputs | Accept TTL/CMOS-compatible signals; drive internal delay paths separately |
| OUT1–OUT3 | Buffered delay outputs | Deliver 15 ns delayed copies with rail-to-rail swing and low skew |
| VCC | Positive supply | +3V supply pin; decoupling required within 10 mm of pin for noise immunity |
| GND | Ground reference | Common return for all inputs, outputs, and internal circuitry; must be low-impedance |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon construction | Eliminates aging, humidity, and temperature drift inherent in RC or analog delay solutions |
| Leading & trailing edge precision | Maintains input duty cycle integrity - critical for clock/data alignment in high-speed interfaces |
| Three independent buffered delays | Enables parallel timing adjustment without cross-talk or shared loading effects |
| Industrial temperature operation | Guaranteed 15 ns delay performance from -40°C to +85°C - suitable for embedded control and test systems |
| 3V-only operation | Optimized for low-voltage logic domains; avoids level-shifting complexity in 3.3V systems |
Applications
| High-Speed Clock Distribution | FPGA I/O Timing Calibration |
|---|---|
Use Scenario: Distributing a master clock to multiple synchronous logic blocks while compensating for trace-length skew. IC Role / Device Role / Timing Role: Fixed 15 ns delay element inserted in clock paths to align arrival times across receivers. Use Value: Eliminates need for PCB trace tuning or programmable delay ICs; reduces jitter accumulation vs. cascaded buffers. | Use Scenario: Calibrating input capture windows for high-speed parallel I/O (e.g., DDR source-synchronous interfaces) on Xilinx or Intel FPGAs. IC Role / Device Role / Timing Role: Delaying reference clocks or data-strobe signals to match internal FPGA timing margins. Use Value: Enables deterministic setup/hold timing at 200+ MHz without dynamic calibration logic or PLL-based deskew. |
| Digital Test Equipment Signal Conditioning | Industrial PLC Input Synchronization |
Use Scenario: Introducing precise, repeatable delays into stimulus signals for automated boundary-scan or functional test vectors. IC Role / Device Role / Timing Role: Deterministic delay generator for generating phase-shifted test patterns with nanosecond resolution. Use Value: Replaces expensive arbitrary waveform generators for fixed-delay test cases; improves repeatability over temperature. | Use Scenario: Synchronizing asynchronous sensor inputs (e.g., encoder quadrature, limit switches) to a central control loop clock. IC Role / Device Role / Timing Role: Debounce-free delay element that aligns edge-triggered inputs to system timing domain. Use Value: Avoids software-based filtering latency; provides hardware-level deterministic response within 15 ns window. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135LZ-12+ | 12 ns nominal delay (vs. 15 ns); same package, tolerance, and electrical specs | Suitable where tighter timing budget requires shorter fixed delay | Select when system-level timing analysis confirms 3 ns reduction improves margin without violating hold constraints |
| DS1135LZ-20+ | 20 ns nominal delay; identical architecture, package, and thermal/voltage stability | Used when longer propagation delay is needed for signal alignment or setup margin expansion | Choose when interconnect skew exceeds 15 ns or when additional safety margin is required for worst-case voltage/temp corners |
Compared with DS1135LZ-12+ and DS1135LZ-20+, the DS1135LZ-15+ provides the optimal fixed delay for systems requiring exact 15 ns compensation-balancing setup/hold margins without over-delaying critical paths or under-compensating for board-level skew.
Availability
DS1135LZ-15+ is available at Aetrix Electronics and suitable for high-speed clock distribution, FPGA I/O calibration, and digital test equipment requiring stable component supply and guaranteed nanosecond-level timing accuracy.
Supply support for DS1135LZ-15+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, communications, and computing applications, emphasizing reliability, integration, and performance.
The DS1135L series belongs to Maxim's high-speed timing portfolio, engineered specifically for deterministic, low-drift fixed-delay applications in digital systems where consistency across voltage and temperature is non-negotiable.
FAQ
What is the guaranteed delay accuracy of DS1135LZ-15+ over its full operating temperature range?
The DS1135LZ-15+ guarantees ±4.0 ns total delay variation (tPLH/tPHL) across -40°C to +85°C and 2.7 V to 3.6 V supply. This includes initial tolerance (±1.0 ns) plus additional drift due to temperature and voltage changes, ensuring predictable 15 ns timing in industrial environments without recalibration.
Does DS1135LZ-15+ require external components or configuration to operate?
No. The DS1135LZ-15+ is a fully self-contained, fixed-delay device requiring only VCC and GND connections. It needs no external resistors, capacitors, or programming; delay value is factory-trimmed and immutable. Power-up occurs within 1 ms, and outputs begin delivering 15 ns delayed signals immediately thereafter.
Can DS1135LZ-15+ replace DS1033 in existing designs?
Yes - DS1135LZ-15+ is explicitly designated as the recommended replacement for DS1033. It offers identical pinout, improved 3V operation, tighter delay tolerance (±1.0 ns vs. ±5 ns), and enhanced temperature stability. No PCB or firmware changes are required, though supply voltage should be confirmed at 3.3 V ±10%.
What is the maximum input frequency supported by DS1135LZ-15+?
The DS1135LZ-15+ supports input pulse periods down to 2× the delay value (i.e., ≥30 ns period), corresponding to a maximum fundamental frequency of ~33 MHz. Its 2.0–2.5 ns output rise/fall times enable clean edge reproduction for signals up to 200+ MHz harmonics, provided input pulse width meets tWI ≥15 ns.
Is DS1135LZ-15+ compatible with 5V logic families?
No. DS1135LZ-15+ is strictly a 3V device (2.7–3.6 V operation). Its VIH threshold is 2.0 V minimum, and absolute maximum pin voltage is +6.0 V - but sustained 5V input violates DC specifications and risks latch-up or parametric shift. Level-shifting is required for interfacing with 5V systems.
DS1135LZ-15+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 15ns
- Tap Increment:
- -
- Available Total Delays:
- 15ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135LZ-15+ FAQ
1.How can I place an order for DS1135LZ-15+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LZ-15+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LZ-15+ reliable?
The price and inventory of DS1135LZ-15+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LZ-15+ is usually 5 days.
3.What payment methods are accepted for DS1135LZ-15+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LZ-15+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LZ-15+?
DS1135LZ-15+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LZ-15+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LZ-15+?
For technical support, including DS1135LZ-15+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LZ-15+ requirements.
6.How does Aetrix verify that DS1135LZ-15+ is sourced from the original manufacturer or authorized distributors?
All DS1135LZ-15+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LZ-15+ meets industry standards.
7.What is the process for return or replacement of DS1135LZ-15+?
All DS1135LZ-15+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LZ-15+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LZ-15+ part is unused and in its original packaging.
Return procedure for DS1135LZ-15+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LZ-15+ Tags

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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