Analog Devices Inc./Maxim Integrated DS1135LZ-15
- Part No.:
- DS1135LZ-15
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135LZ-15.pdf
- Description:
- IC DELAY LINE 15NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:8,781
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Product details
Overview
DS1135LZ-15 from Maxim Integrated is a 3V, 3-in-1 high-speed silicon delay line delivering precise 15 ns propagation delays (tPLH/tPHL) across all three independent buffered outputs, with ±1.0 ns initial tolerance and ±2.5 ns tolerance over -40°C to +85°C, used in clock skew management and digital signal alignment in industrial control systems.
For engineers reviewing the DS1135LZ-15 datasheet, DS1135LZ-15 pinout, DS1135LZ-15 application, or DS1135LZ-15 equivalent, this page provides verified timing accuracy, SO-8 package compatibility, temperature-stable delay performance, and direct replacement guidance for legacy DS1033-based designs.
Technical Context
The DS1135LZ-15 implements three fully independent, logic-buffered delay paths in a single monolithic silicon IC, each preserving input signal symmetry via matched leading and trailing edge accuracy. Its all-silicon architecture eliminates quartz aging and thermal hysteresis issues inherent in crystal-based solutions.
It operates strictly within 2.7V–3.6V supply range and guarantees sub-nanosecond edge fidelity under industrial temperature extremes. Delay stability is characterized per Table 1 with explicit tPLH/tPHL values, not average or typical-only specs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 15 ns (tPLH/tPHL), identical across OUT1–OUT3, enabling synchronized multi-path timing alignment |
| Initial delay tolerance | ±1.0 ns at +25°C/3.3V - ensures tight batch-to-batch matching without calibration |
| Tolerance over temp/volt | ±2.5 ns (-40°C to +85°C, 2.7V–3.6V) - supports unregulated 3V rails in harsh environments |
| Supply voltage range | 2.7V to 3.6V - compatible with modern low-voltage FPGA I/O and microcontroller domains |
| Output rise/fall time | 2.0–2.5 ns - maintains signal integrity for >200 MHz digital edges without added termination |
| Power-up time | 1 ms - enables immediate delay stabilization after cold start, no warm-up delay required |
| Input capacitance | 10 pF - minimizes loading on preceding driver stages in high-speed fanout chains |
Pinout & Package
DS1135LZ-15 is housed in an 8-pin SOIC (150-mil) package, RoHS-compliant (Z suffix), with standard JEDEC MS-012AC outline and 90-0096 land pattern.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Dedicated input signals for each delay path | Independent logic-level inputs accepting TTL/CMOS-compatible thresholds; no shared internal routing |
| OUT1, OUT2, OUT3 | Buffered delayed outputs | Each delivers identical 15 ns delay with matched tPLH/tPHL; drives one 74F04-equivalent load |
| VCC | +3V power supply | Single-supply operation only; decoupling required within 10 mm of pin per layout guidelines |
| GND | Ground reference | Common return for all inputs, outputs, and internal circuitry; must be low-impedance plane |
Key Features
| Feature | Design Value |
|---|---|
| Precision edge-aligned delay | Matched tPLH/tPHL preserves input duty cycle symmetry - critical for clock forwarding and DDR strobe alignment |
| All-silicon construction | No quartz aging, no frequency drift over lifetime - eliminates recalibration in sealed industrial enclosures |
| Three independent delay paths | Enables simultaneous skew correction across multiple data lanes (e.g., parallel bus, ADC sampling clocks) |
| Vapor-phase & IR reflow compatible | Rated for +260°C reflow peak - supports automated SMT assembly without derating or special profiles |
| Industrial temperature support | Guaranteed 15 ns delay stability across -40°C to +85°C - validated per Table 1, not extrapolated |
Applications
| Industrial PLC Timing Alignment | FPGA Clock Skew Compensation |
|---|---|
Use Scenario: Synchronizing distributed I/O scan cycles across multiple backplane modules in a programmable logic controller. IC Role / Device Role / Timing Role: DS1135LZ-15 provides deterministic 15 ns delay to align asynchronous sensor input capture clocks with master scan timing. Use Value: Eliminates metastability in cross-clock-domain sampling by guaranteeing sub-2.5 ns delay variation across full industrial temperature range. |
Use Scenario: Matching trace delays between FPGA configuration clock and JTAG TCK in high-density BGA packages. IC Role / Device Role / Timing Role: DS1135LZ-15 inserts calibrated delay on TCK path to meet setup/hold timing at boundary-scan cells. Use Value: Achieves 100% JTAG chain reliability without PCB redesign, leveraging ±2.5 ns worst-case tolerance. |
| Motor Drive Gate Signal Conditioning | Digital Audio Sample Clock Alignment |
Use Scenario: Aligning complementary PWM signals driving high-side/low-side IGBTs in servo inverters. IC Role / Device Role / Timing Role: DS1135LZ-15 applies matched delay to one leg's gate drive to prevent shoot-through during transitions. Use Value: Maintains precise 15 ns offset with <100 ps edge jitter, directly improving inverter efficiency and thermal margin. |
Use Scenario: Equalizing propagation delay between SPDIF receiver clock and DAC master clock in professional audio interfaces. IC Role / Device Role / Timing Role: DS1135LZ-15 compensates for PCB trace mismatch between two clock domains feeding a dual-channel DAC. Use Value: Reduces inter-channel phase error to <0.1° at 96 kHz, meeting AES11 jitter compliance requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1033Z-15+ | Higher active current (15 mA vs. 10 mA), wider delay tolerance (±3.0 ns over -40°C to +85°C), same SO-8 package | Limited to commercial temp range in most variants; less stable under voltage fluctuation | Choose DS1033Z-15+ only if legacy board footprint reuse is mandatory and industrial temp stability is not required. |
| SY100EL15ZC | ECL-compatible (−5.2V supply), 1.2 ns faster rise/fall time, but requires level translation for 3V systems | Designed for RF/datacom clock distribution; lacks guaranteed symmetry preservation at 3V | Prefer SY100EL15ZC only when integrating into existing ECL infrastructure with strict <2 ns edge jitter budgets. |
Compared with DS1033Z-15+ and SY100EL15ZC, the DS1135LZ-15 uniquely combines 3V operation, industrial temperature guarantee, and matched leading/trailing edge delay in a drop-in SO-8 package-making it the sole option for new 3V embedded timing designs requiring long-term stability without level-shifting overhead.
Availability
DS1135LZ-15 is available at Aetrix Electronics and suitable for industrial PLC timing alignment, FPGA clock skew compensation, and motor drive gate signal conditioning requiring stable component supply across extended temperature ranges and multi-year production cycles.
Supply support for DS1135LZ-15 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, automotive, and communications applications, with emphasis on reliability and parametric guarantee.
The DS1135L series was developed specifically for high-stability, low-power digital timing in space-constrained industrial systems where quartz-based delay solutions fail due to shock sensitivity and aging drift.
FAQ
What is the guaranteed delay accuracy of DS1135LZ-15 over its full operating temperature range?
The DS1135LZ-15 guarantees ±2.5 ns delay variation (tPLH/tPHL) across −40°C to +85°C at VCC = 2.7V–3.6V, as specified in Table 1 of the official datasheet. This includes both leading and trailing edge measurements referenced to the 1.5V threshold. The value is measured, not extrapolated, and applies identically to all three outputs.
Can DS1135LZ-15 replace DS1033Z-15+ in an existing design without layout changes?
Yes - DS1135LZ-15 uses the identical 8-pin SOIC (150-mil) package and pinout as DS1033Z-15+, making it a direct physical replacement. However, DS1135LZ-15 draws less current (10 mA vs. 15 mA) and offers tighter delay tolerance (±2.5 ns vs. ±3.0 ns), so no PCB modifications are needed, but decoupling may be optimized for lower noise.
Does DS1135LZ-15 require external termination resistors on its outputs?
No - DS1135LZ-15 is designed to drive one 74F04-equivalent load (≈15 pF capacitive load) directly, as confirmed in the AC Electrical Characteristics section. External termination is unnecessary unless driving longer traces (>5 cm) or multiple loads, in which case series source termination at the driver may be applied per standard high-speed layout practice.
Is DS1135LZ-15 qualified for reflow soldering using lead-free processes?
Yes - DS1135LZ-15 carries the "Z" suffix indicating RoHS-compliance and is rated for lead-free reflow up to +260°C (per JEDEC J-STD-020), including vapor-phase and infrared methods. The device meets Maxim's qualified process flow for Pb-free assembly without derating or special profile adjustments.
How does DS1135LZ-15 preserve input signal symmetry between rising and falling edges?
DS1135LZ-15 achieves leading and trailing edge precision through matched internal buffer paths and symmetric output stage design, ensuring tPLH and tPHL are equal within ±0.2 ns across all conditions. This symmetry preservation is explicitly tested and guaranteed per Note 3 in Table 1, directly supporting applications like clock forwarding where duty cycle integrity is essential.
DS1135LZ-15 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 15ns
- Tap Increment:
- -
- Available Total Delays:
- 15ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135LZ-15 FAQ
1.How can I place an order for DS1135LZ-15 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LZ-15 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LZ-15 reliable?
The price and inventory of DS1135LZ-15 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LZ-15 is usually 5 days.
3.What payment methods are accepted for DS1135LZ-15?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LZ-15 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LZ-15?
DS1135LZ-15 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LZ-15 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LZ-15?
For technical support, including DS1135LZ-15 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LZ-15 requirements.
6.How does Aetrix verify that DS1135LZ-15 is sourced from the original manufacturer or authorized distributors?
All DS1135LZ-15 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LZ-15 meets industry standards.
7.What is the process for return or replacement of DS1135LZ-15?
All DS1135LZ-15 units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LZ-15, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LZ-15 part is unused and in its original packaging.
Return procedure for DS1135LZ-15:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LZ-15 Tags

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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