Analog Devices Inc./Maxim Integrated DS1135LZ-15/T&R
- Part No.:
- DS1135LZ-15/T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135LZ-15/T&R.pdf
- Description:
- IC DELAY LINE 15NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,952
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1135LZ-15/T&R from Maxim Integrated is a 3V, 8-pin SO (150-mil) all-silicon delay line delivering three independent buffered delays of precisely 15 ns each (tPLH/tPHL), with ±1.0 ns initial tolerance and ±2.5 ns tolerance over -40°C to +85°C. It preserves input signal symmetry via leading/trailing edge precision and supports industrial temperature operation with 2.7V–3.6V supply range.
For engineers reviewing the DS1135LZ-15/T&R datasheet, DS1135LZ-15/T&R pinout, DS1135LZ-15/T&R application, or DS1135LZ-15/T&R equivalent, this device serves as a high-speed, low-power timing solution for clock skew management, pulse width adjustment, and signal alignment in FPGA/ASIC interface circuits where deterministic nanosecond-level delay stability is critical.
Technical Context
The DS1135LZ-15/T&R implements three identical, fully buffered delay paths in a single monolithic silicon structure-no external components required. Each path delivers matched 15 ns propagation delay (tPLH = tPHL = 15 ns) with sub-nanosecond edge accuracy, enabling precise synchronization across multiple signal lanes.
Its logic-level compatibility (VIH ≥ 2.0 V, VIL ≤ 0.8 V), 2.5 ns max output rise/fall time, and 1 ms power-up time support integration into 3V high-speed digital systems without level-shifting or additional conditioning circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 15 ns (tPLH/tPHL), matched across all three outputs for skew-critical signal alignment |
| Initial delay tolerance | ±1.0 ns at +25°C, 3.3 V - enables tight timing budget allocation without guardbanding |
| Temp/voltage tolerance | ±2.5 ns over -40°C to +85°C and 2.7V–3.6V - ensures stable delay under real-world operating conditions |
| Supply voltage range | 2.7 V to 3.6 V - compatible with modern 3V logic families and low-power system rails |
| Output rise/fall time | ≤2.5 ns (20%–80%) - maintains signal integrity for >200 MHz pulse applications |
| Power-up time | 1 ms - allows predictable initialization after power-on or reset in embedded control sequences |
Pinout & Package
DS1135LZ-15/T&R is housed in an 8-pin SOIC package (150-mil width, outline 21-0041), RoHS-compliant (Z suffix), vapor-phase and IR-reflow solderable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Independent logic inputs | Accept TTL/CMOS-compatible signals; each drives one dedicated delay path |
| OUT1, OUT2, OUT3 | Buffered delay outputs | Provide 15 ns delayed, rail-to-rail logic outputs with 2.5 ns edge speed |
| VCC | Positive supply | Single 2.7–3.6 V rail powers all three delay paths and buffers simultaneously |
| GND | Ground reference | Common return for inputs, outputs, and internal circuitry; decoupling required near pin |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon construction | Eliminates aging, drift, and reliability risks associated with RC or LC analog delay elements |
| Three independent buffered delays | Enables concurrent delay of separate control/data lines without crosstalk or loading effects |
| Leading and trailing edge precision | Maintains 50% duty cycle integrity across full temperature/voltage range for clock distribution |
| Industrial temperature range | Validated operation from -40°C to +85°C - suitable for automotive body electronics and industrial PLCs |
Applications
| High-Speed FPGA Clock Alignment | Pulse Width Adjustment in Motor Control |
|---|---|
Use Scenario: Aligning clock edges between FPGA I/O banks to meet setup/hold timing across multi-lane interfaces. IC Role / Device Role / Timing Role: Provides deterministic, matched 15 ns delay on three parallel clock or strobe signals. Use Value: Eliminates inter-bank skew without custom PCB trace tuning or external delay networks. |
Use Scenario: Adjusting PWM pulse width in BLDC motor gate drivers to compensate for MOSFET switching latency. IC Role / Device Role / Timing Role: Delays enable/disable signals to synchronize gate drive activation with current sensing windows. Use Value: Enables precise dead-time insertion and prevents shoot-through without microcontroller overhead. |
| ASIC Test Pattern Synchronization | Industrial Sensor Signal Conditioning |
Use Scenario: Time-aligning test stimulus and response capture channels in ATE systems for multi-pin DUTs. IC Role / Device Role / Timing Role: Delays reference clocks or trigger signals to match propagation delays in fixture wiring. Use Value: Improves pattern correlation accuracy by compensating for fixed interconnect skew up to 15 ns. |
Use Scenario: Introducing calibrated delay between analog sensor output and ADC sampling trigger in vibration monitoring nodes. IC Role / Device Role / Timing Role: Matches analog signal path latency to digital control loop timing requirements. Use Value: Ensures phase-coherent sampling of transient events without firmware-based delay compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-output silicon delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1035Z-15+ | Higher active current (15 mA vs. 10 mA), wider delay tolerance (±3.0 ns over -40°C to +85°C) | Legacy 5V-compatible design; less suitable for battery-powered 3V systems | Select DS1135LZ-15/T&R for lower power and tighter delay stability in new 3V designs |
| MAX9012EUA+ | Comparator-based delay generator with adjustable delay (not fixed 15 ns); requires external RC network | Used for variable-delay applications like window detection or adaptive timing, not fixed-skew correction | Choose DS1135LZ-15/T&R when deterministic, factory-trimmed, and temperature-stable 15 ns delay is required |
Compared with DS1035Z-15+ and MAX9012EUA+, the DS1135LZ-15/T&R delivers superior delay accuracy (±2.5 ns vs. ±3.0 ns), lower supply current (10 mA vs. 15 mA), and guaranteed fixed 15 ns matching-making it optimal for skew-critical, low-power 3V timing applications where calibration-free operation is mandatory.
Availability
DS1135LZ-15/T&R is available at Aetrix Electronics and suitable for high-speed FPGA interface design, industrial motor control systems, ASIC test equipment, and sensor signal conditioning requiring stable component supply and guaranteed 15 ns delay performance.
Supply support for DS1135LZ-15/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, automotive, and communications applications, emphasizing reliability, integration, and performance.
The DS1135L series was developed as a low-power, 3V upgrade to the DS1033 family-targeting high-speed digital systems needing deterministic, temperature-stable delay without external components.
FAQ
What is the exact delay value and tolerance of DS1135LZ-15/T&R over industrial temperature?
The DS1135LZ-15/T&R provides a nominal delay of 15 ns per output (tPLH/tPHL), with ±2.5 ns tolerance over the full -40°C to +85°C range and 2.7V–3.6V supply. This specification is guaranteed per Maxim's datasheet Table 1 and applies identically to all three outputs, ensuring matched delay paths for skew-sensitive applications.
Is DS1135LZ-15/T&R pin-compatible with DS1033 series devices?
No, DS1135LZ-15/T&R is not pin-compatible with DS1033 devices. While both are 3-output delay lines, DS1135LZ-15/T&R uses an 8-pin SO package with dedicated IN1–IN3 and OUT1–OUT3 pins, whereas DS1033 variants use 14-pin packages with different pin assignments and logic configurations. Board redesign is required for replacement.
Does DS1135LZ-15/T&R require external components for operation?
No, DS1135LZ-15/T&R operates as a fully self-contained delay element. Only a 0.1 µF ceramic bypass capacitor between VCC and GND (placed near the package) is recommended. No resistors, capacitors, or trimming components are needed-its 15 ns delay is factory-trimmed and temperature-compensated within the all-silicon die.
What is the maximum input frequency supported by DS1135LZ-15/T&R?
DS1135LZ-15/T&R supports input pulse periods down to 2× the delay value (i.e., ≥30 ns period), corresponding to a maximum fundamental frequency of ~33 MHz. Its 2.5 ns output rise/fall time and 100 ns minimum input pulse width (per datasheet AC specs) ensure reliable operation with fast-edged digital waveforms in high-speed logic environments.
Can DS1135LZ-15/T&R be used with 2.5V or 3.3V supply rails?
Yes, DS1135LZ-15/T&R is fully specified for operation across 2.7V to 3.6V. It functions reliably at 2.5V (slightly below min spec) with minor degradation in delay stability and output drive strength, but for guaranteed performance-including ±2.5 ns tolerance and 8 mA low-level output drive-the supply must remain within the 2.7V–3.6V range per the datasheet.
DS1135LZ-15/T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 15ns
- Tap Increment:
- -
- Available Total Delays:
- 15ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135LZ-15/T&R FAQ
1.How can I place an order for DS1135LZ-15/T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LZ-15/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LZ-15/T&R reliable?
The price and inventory of DS1135LZ-15/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LZ-15/T&R is usually 5 days.
3.What payment methods are accepted for DS1135LZ-15/T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LZ-15/T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LZ-15/T&R?
DS1135LZ-15/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LZ-15/T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LZ-15/T&R?
For technical support, including DS1135LZ-15/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LZ-15/T&R requirements.
6.How does Aetrix verify that DS1135LZ-15/T&R is sourced from the original manufacturer or authorized distributors?
All DS1135LZ-15/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LZ-15/T&R meets industry standards.
7.What is the process for return or replacement of DS1135LZ-15/T&R?
All DS1135LZ-15/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LZ-15/T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LZ-15/T&R part is unused and in its original packaging.
Return procedure for DS1135LZ-15/T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LZ-15/T&R Tags

-
LTC6994CS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994CDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRPBF
Analog Devices Inc.

-
LTC6994IDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-1#TRMPBF
Analog Devices Inc.

-
DS1124U-25+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
