Analog Devices Inc./Maxim Integrated DS1135LZ-25+
- Part No.:
- DS1135LZ-25+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135LZ-25+.pdf
- Description:
- IC DELAY LINE 25NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:200
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Product details
Overview
DS1135LZ-25+ from Maxim Integrated is a 3V, 3-in-1 high-speed silicon delay line delivering precise 25 ns propagation delay on all three independent buffered outputs (tPLH/tPHL = 25/25/25 ns), with ±1.5 ns initial tolerance and ±5.0 ns total variation over -40°C to +85°C. It preserves input signal symmetry via leading/trailing edge accuracy and is used in high-speed digital timing alignment, clock deskewing, and pulse width adjustment circuits.
For engineers reviewing the DS1135LZ-25+ datasheet, DS1135LZ-25+ pinout, DS1135LZ-25+ application, or DS1135LZ-25+ equivalent, this page provides verified timing parameters, SO-8 package layout, industrial temperature support, 3V operation constraints, and direct alternatives for delay-line replacement in synchronous logic systems.
Technical Context
The DS1135LZ-25+ implements three identical, fully buffered delay paths in a single monolithic silicon IC-no external components required. Each path guarantees matched tPLH and tPHL delays of exactly 25 ns under nominal conditions (VCC = 3.3 V, TA = +25°C), with symmetrical rise/fall time control (tOR/tOF ≤ 2.5 ns).
It operates across 2.7 V–3.6 V supply range and supports full industrial temperature range (-40°C to +85°C) with specified delay stability. Input-to-output delay is measured at 1.5 V crossing point, and power-up time is guaranteed ≤1 ms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 25 ns (tPLH/tPHL), matched across all three channels for synchronous signal alignment |
| Initial delay tolerance | ±1.5 ns at +25°C, 3.3 V - sets baseline precision before environmental drift |
| Delay variation over temp/volt | ±5.0 ns from -40°C to +85°C and 2.7–3.6 V - defines worst-case timing budget margin |
| Rise/fall time | ≤2.5 ns (20%–80%) - ensures minimal signal distortion in fast-edge applications |
| Supply voltage range | 2.7 V to 3.6 V - compatible with modern 3V logic families without level shifting |
| Power-up time | ≤1 ms - enables reliable initialization in power-cycled embedded systems |
| Input capacitance | 10 pF typical - minimizes loading on preceding driver stage |
Pinout & Package
DS1135LZ-25+ is housed in an 8-pin SOIC package (150-mil width, outline 21-0041), RoHS-compliant (Z suffix), vapor-phase and IR-reflow solderable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Dedicated input signals | Three independent TTL/CMOS-compatible inputs accepting 0–3.6 V swing; each drives one delay path |
| OUT1, OUT2, OUT3 | Buffered delay outputs | Three low-skew, rail-to-rail outputs with 25 ns fixed delay; each loaded to 15 pF per spec |
| VCC | Positive supply | +3V core supply pin; must be decoupled locally due to 10 mA active current draw |
| GND | Ground reference | Common return for all inputs, outputs, and internal circuitry; requires low-impedance PCB connection |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates aging, temperature hysteresis, and mechanical failure modes inherent in LC or SAW delay lines |
| Precision edge matching | Identical tPLH and tPHL (25 ns each) preserves 50% duty cycle integrity across all outputs |
| Industrial temperature support | Guaranteed 25 ns delay performance from -40°C to +85°C - suitable for automotive and industrial control |
| 3V-only operation | Optimized for 3.3 V systems; no 5V compatibility - reduces noise coupling and simplifies power domain partitioning |
| SO-8 footprint compatibility | Standard 150-mil SOIC layout enables drop-in replacement for legacy DS1033/DS1035 designs |
Applications
| High-Speed Clock Deskewing | Digital Signal Alignment |
|---|---|
Use Scenario: Aligning multiple clock domains in FPGA-based data acquisition systems where skew between sampling clocks must be <50 ps. IC Role / Device Role / Timing Role: DS1135LZ-25+ provides deterministic, matched 25 ns delay on three parallel clock paths to compensate for PCB trace length mismatches. Use Value: Enables simultaneous multi-channel sampling with sub-nanosecond inter-channel timing coherence. | Use Scenario: Synchronizing enable pulses across three independent memory banks in a DDR controller interface. IC Role / Device Role / Timing Role: DS1135LZ-25+ delivers identical 25 ns delay to each bank's chip-select signal, eliminating setup/hold violations. Use Value: Increases memory bandwidth utilization by removing timing guardbands imposed by unmatched delays. |
| Pulse Width Adjustment | Logic Glitch Suppression |
Use Scenario: Extending narrow reset pulses generated by microcontroller GPIOs to meet minimum width requirements of peripheral ICs. IC Role / Device Role / Timing Role: DS1135LZ-25+ stretches input pulses by precisely 25 ns on any selected channel while preserving edge fidelity. Use Value: Eliminates need for RC networks or additional logic gates, reducing BOM count and board area. | Use Scenario: Removing short-duration metastability-induced glitches on asynchronous interrupt lines feeding an ARM Cortex-M4 core. IC Role / Device Role / Timing Role: DS1135LZ-25+ filters sub-25 ns transients by delaying and re-sampling the signal through its clean buffered path. Use Value: Prevents spurious interrupt triggering without introducing variable latency or software overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar delay-line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1035Z-25+ | Same 25 ns delay, but higher initial tolerance (±3.0 ns) and wider temp drift (±8.0 ns over -40°C to +85°C) | Limited to commercial-temp applications where tighter delay stability is not required | Select DS1035Z-25+ only if cost sensitivity outweighs timing precision needs |
| MAX9992ETE+ | Programmable 0–63 ns delay in 1 ns steps; 10-bit SPI interface; 16-pin TQFN package | Requires configuration interface and firmware support; suited for adaptive delay tuning | Choose MAX9992ETE+ when dynamic delay adjustment or multi-channel programmability is essential |
Compared with DS1035Z-25+, DS1135LZ-25+ offers superior delay accuracy and thermal stability; versus MAX9992ETE+, it trades programmability for lower system complexity, smaller footprint, and zero configuration overhead.
Availability
DS1135LZ-25+ is available at Aetrix Electronics and suitable for high-speed digital test equipment, industrial motion controllers, FPGA-based prototyping platforms, and medical imaging timing subsystems requiring stable component supply and long-term obsolescence management.
Supply support for DS1135LZ-25+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, communications, and computing applications, emphasizing reliability, integration, and performance.
The DS1135L series was developed to replace aging discrete delay solutions with a robust, temperature-stable, all-silicon alternative optimized for 3V high-speed digital timing alignment.
FAQ
What is the guaranteed delay accuracy of DS1135LZ-25+ over its full operating temperature range?
The DS1135LZ-25+ guarantees ±5.0 ns delay variation over the industrial temperature range of -40°C to +85°C and supply voltage range of 2.7 V to 3.6 V. This includes both initial tolerance (±1.5 ns at +25°C) and additional drift due to temperature and voltage changes. All three outputs maintain identical delay values within this specification, ensuring channel-to-channel matching critical for synchronous systems.
Can DS1135LZ-25+ operate from a 5V supply?
No, DS1135LZ-25+ is strictly a 3V device with absolute maximum VCC rating of +6.0 V but specified operation only from 2.7 V to 3.6 V. Applying 5V violates the DC electrical specifications and may cause permanent damage or unpredictable timing behavior. For 5V systems, consider legacy DS1035 variants or level-shifting interfaces - DS1135LZ-25+ itself must be powered from a regulated 3.3 V source.
Is DS1135LZ-25+ pin-compatible with DS1033Z-25+?
Yes, DS1135LZ-25+ uses the same 8-pin SOIC (150-mil) package and identical pinout as DS1033Z-25+: IN1–IN3, GND, VCC, OUT1–OUT3. It is explicitly designated as a recommended replacement in the datasheet, offering improved delay accuracy (±1.5 ns vs. ±3.0 ns) and lower power consumption while maintaining full mechanical and electrical compatibility.
What is the maximum input frequency supported by DS1135LZ-25+?
DS1135LZ-25+ does not specify a maximum input frequency directly, but AC characteristics require input pulse width (tWI) to be ≥100% of the delay value (i.e., ≥25 ns). With minimum pulse width of 25 ns and 50% duty cycle, the maximum fundamental frequency is 20 MHz. Higher harmonics are supported due to 2.5 ns rise/fall times, but sustained operation above 20 MHz requires validation of pulse integrity and load conditions per application.
Does DS1135LZ-25+ require external termination or biasing resistors?
No, DS1135LZ-25+ features internally terminated, CMOS-compatible inputs and push-pull outputs designed to drive standard logic loads (e.g., one 74F04 input gate, ~15 pF). External termination is unnecessary unless driving long traces or mismatched transmission lines. The device specifies 50 Ω source impedance test conditions for characterization, but actual use requires no pull-up/down resistors or series terminations under typical PCB routing practices.
DS1135LZ-25+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 25ns
- Tap Increment:
- -
- Available Total Delays:
- 25ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135LZ-25+ FAQ
1.How can I place an order for DS1135LZ-25+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LZ-25+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LZ-25+ reliable?
The price and inventory of DS1135LZ-25+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LZ-25+ is usually 5 days.
3.What payment methods are accepted for DS1135LZ-25+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LZ-25+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LZ-25+?
DS1135LZ-25+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LZ-25+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LZ-25+?
For technical support, including DS1135LZ-25+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LZ-25+ requirements.
6.How does Aetrix verify that DS1135LZ-25+ is sourced from the original manufacturer or authorized distributors?
All DS1135LZ-25+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LZ-25+ meets industry standards.
7.What is the process for return or replacement of DS1135LZ-25+?
All DS1135LZ-25+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LZ-25+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LZ-25+ part is unused and in its original packaging.
Return procedure for DS1135LZ-25+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LZ-25+ Tags

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LTC6994CS6-1#TRMPBF
Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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LTC6994IS6-1#TRPBF
Analog Devices Inc.

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Analog Devices Inc.

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LTC6994IS6-2#TRMPBF
Analog Devices Inc.

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LTC6994HS6-1#TRPBF
Analog Devices Inc.

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Analog Devices Inc.

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LTC6994HS6-2#TRMPBF
Analog Devices Inc.

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LTC6994HDCB-2#TRMPBF
Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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