Analog Devices Inc./Maxim Integrated DS1135LZ-25+T&R
- Part No.:
- DS1135LZ-25+T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135LZ-25+T&R.pdf
- Description:
- IC DELAY LINE 25NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,442
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Product details
Overview
DS1135LZ-25+T&R from Maxim Integrated is a 3V, 3-in-1 high-speed silicon delay line delivering precise 25 ns propagation delay on all three independent buffered outputs (tPLH/tPHL = 25/25/25 ns), with ±1.5 ns initial tolerance and ±5.0 ns total tolerance over -40°C to +85°C, used in clock skew management and digital signal alignment in industrial control and test equipment.
For engineers reviewing the DS1135LZ-25+T&R datasheet, DS1135LZ-25+T&R pinout, DS1135LZ-25+T&R application, or DS1135LZ-25+T&R equivalent, key selection criteria include guaranteed edge-aligned delay accuracy, 3.3 V supply compatibility, SO-8 (150-mil) package footprint, and replacement suitability for legacy DS1033-based timing circuits.
Technical Context
The DS1135LZ-25+T&R implements three identical, fully buffered CMOS delay paths in a single monolithic silicon IC, each preserving input signal symmetry via matched leading/trailing edge propagation (tPLH ≈ tPHL). It operates across 2.7 V–3.6 V with no external components required.
Its architecture eliminates quartz-based drift and aging effects while maintaining sub-nanosecond edge fidelity-critical for synchronous sampling, pulse width matching, and deterministic timing in high-reliability embedded systems where thermal stability and reflow compatibility are mandatory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 25 ns (tPLH/tPHL), identical across all three outputs for synchronized signal alignment |
| Initial delay tolerance | ±1.5 ns at +25°C, 3.3 V - enables tight setup/hold margin planning without calibration |
| Temp/voltage tolerance | ±5.0 ns over -40°C to +85°C and 2.7 V–3.6 V - ensures stable timing in unregulated industrial environments |
| Supply voltage range | 2.7 V–3.6 V - compatible with modern 3.3 V logic families and low-power system rails |
| Rise/fall time | 2.0–2.5 ns - preserves fast-edge integrity for >100 MHz digital signal paths |
| Power-up time | 1 ms - allows predictable initialization after power-on reset without external sequencing |
Pinout & Package
DS1135LZ-25+T&R is housed in an 8-pin SOIC (150-mil) package, RoHS-compliant, vapor-phase and IR-reflow solderable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1–IN3 | Dedicated input signals | Three independent TTL/CMOS-compatible inputs accepting 0.0 V–3.0 V pulses; no internal crosstalk coupling |
| OUT1–OUT3 | Buffered delay outputs | Three matched-delay outputs driving 74F04-equivalent loads (15 pF), edge-aligned to inputs |
| VCC | +3V supply rail | Single 2.7 V–3.6 V supply powers all three delay paths; decoupling recommended near pin |
| GND | Ground reference | Common return for all inputs, outputs, and internal circuitry; critical for delay stability |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates quartz aging, shock sensitivity, and frequency drift-ideal for long-life industrial deployments |
| Precision edge matching (tPLH ≈ tPHL) | Maintains input waveform symmetry; prevents duty cycle distortion in clock distribution networks |
| Three independent buffered delays | Enables parallel timing correction of multiple signal paths without external fanout or buffering |
| Lead-free, RoHS-compliant SO-8 package | Supports automated assembly per JEDEC J-STD-020C; compatible with standard 150-mil SO footprints |
Applications
| Industrial PLC Timing Calibration | Digital Test Equipment Pulse Alignment |
|---|---|
Use Scenario: Synchronizing I/O scan cycles across distributed modules in programmable logic controllers under varying ambient temperatures. IC Role / Device Role / Timing Role: DS1135LZ-25+T&R provides deterministic 25 ns offset to align sensor sampling windows with actuator update triggers. Use Value: Eliminates jitter-induced misreads by guaranteeing ±5.0 ns delay stability across -40°C to +85°C operating range. | Use Scenario: Matching propagation delays between stimulus and measurement channels in automated test systems. IC Role / Device Role / Timing Role: DS1135LZ-25+T&R applies identical 25 ns delay to three independent trigger lines feeding DUT interface logic. Use Value: Ensures simultaneous edge arrival at device-under-test inputs, enabling accurate parametric timing measurements. |
| High-Speed Data Acquisition Clock Skew Correction | Legacy System DS1033 Replacement |
Use Scenario: Compensating for PCB trace length mismatches in multi-channel ADC front-ends using shared sampling clocks. IC Role / Device Role / Timing Role: DS1135LZ-25+T&R inserts calibrated delay into shorter-path clock branches to equalize total path latency. Use Value: Achieves sub-ns inter-channel skew reduction without custom layout or discrete RC networks. | Use Scenario: Upgrading obsolete DS1033-based designs requiring improved temperature stability and lead-free compliance. IC Role / Device Role / Timing Role: DS1135LZ-25+T&R serves as drop-in functional replacement with identical pinout and enhanced 3V operation. Use Value: Maintains existing board layout while improving delay accuracy (±1.5 ns vs. ±5 ns) and extending operational temperature range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1033Z-25+ | 5V-only operation (4.5–5.5 V); ±5 ns initial tolerance; wider temp range (-55°C to +125°C) | Requires level-shifting in 3V systems; higher power consumption; legacy support only | Select only if 5V supply and extended temp range are mandatory and 3V compatibility is not required |
| MAX9992ETE+ | Programmable delay (1–100 ns in 1 ns steps); 3.3 V operation; TQFN-16 package | Offers fine-grained adjustment but requires SPI configuration; no pin compatibility with DS1135LZ-25+T&R | Choose when dynamic delay tuning is needed and board redesign is acceptable |
Compared with DS1033Z-25+, DS1135LZ-25+T&R delivers tighter delay accuracy and lower voltage operation in the same SO-8 footprint; versus MAX9992ETE+, it offers fixed, zero-config delay with simpler integration but no programmability.
Availability
DS1135LZ-25+T&R is available at Aetrix Electronics and suitable for industrial automation, test instrumentation, and data acquisition systems requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant manufacturing.
Supply support for DS1135LZ-25+T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, automotive, and communications applications, emphasizing reliability, integration, and performance under harsh conditions.
The DS1135L series belongs to Maxim's high-stability timing solutions product line, engineered specifically for deterministic digital delay applications where quartz oscillators or RC networks lack repeatability or thermal robustness.
FAQ
What is the guaranteed delay accuracy of DS1135LZ-25+T&R over its full operating temperature range?
The DS1135LZ-25+T&R guarantees ±5.0 ns total delay variation (tPLH/tPHL) across -40°C to +85°C and 2.7 V–3.6 V supply, including initial tolerance, temperature drift, and voltage sensitivity. This specification is measured at the 1.5 V switching threshold and applies identically to all three outputs of DS1135LZ-25+T&R.
Is DS1135LZ-25+T&R pin-compatible with the DS1033 series?
Yes, DS1135LZ-25+T&R uses the same 8-pin SO (150-mil) package and identical pin assignment (IN1–IN3, OUT1–OUT3, VCC, GND) as DS1033Z-25+, enabling direct PCB-level replacement without layout changes-provided the system operates at 3V instead of 5V.
Does DS1135LZ-25+T&R require external passive components for operation?
No, DS1135LZ-25+T&R is a fully self-contained delay line requiring only a 0.1 µF ceramic decoupling capacitor between VCC and GND. No resistors, capacitors, or crystals are needed-its all-silicon design integrates all timing elements internally.
Can DS1135LZ-25+T&R be used with 2.5 V logic inputs?
Yes, DS1135LZ-25+T&R accepts input voltages from -0.5 V to VCC + 0.5 V, supporting 2.5 V logic levels when powered at 3.3 V. Its VIH (2.0 V min) and VIL (0.8 V max) thresholds ensure reliable recognition of 2.5 V CMOS signals without level translation.
What is the maximum output load capacitance supported by DS1135LZ-25+T&R?
DS1135LZ-25+T&R is characterized for 15 pF load capacitance per output, matching one 74F04 input gate. Driving heavier loads (>20 pF) may degrade rise/fall times and delay accuracy; for such cases, external buffer amplification is recommended to maintain DS1135LZ-25+T&R's specified 2.0–2.5 ns edge performance.
DS1135LZ-25+T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 25ns
- Tap Increment:
- -
- Available Total Delays:
- 25ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135LZ-25+T&R FAQ
1.How can I place an order for DS1135LZ-25+T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135LZ-25+T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135LZ-25+T&R reliable?
The price and inventory of DS1135LZ-25+T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135LZ-25+T&R is usually 5 days.
3.What payment methods are accepted for DS1135LZ-25+T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135LZ-25+T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135LZ-25+T&R?
DS1135LZ-25+T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135LZ-25+T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135LZ-25+T&R?
For technical support, including DS1135LZ-25+T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135LZ-25+T&R requirements.
6.How does Aetrix verify that DS1135LZ-25+T&R is sourced from the original manufacturer or authorized distributors?
All DS1135LZ-25+T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135LZ-25+T&R meets industry standards.
7.What is the process for return or replacement of DS1135LZ-25+T&R?
All DS1135LZ-25+T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1135LZ-25+T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135LZ-25+T&R part is unused and in its original packaging.
Return procedure for DS1135LZ-25+T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135LZ-25+T&R Tags

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LTC6994CS6-1#TRMPBF
Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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LTC6994IS6-2#TRMPBF
Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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