Analog Devices Inc./Maxim Integrated DS1135U-10+
- Part No.:
- DS1135U-10+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
DS1135U-10+.pdf
- Description:
- IC DELAY LINE 10NS 8UMAX
- Quantity:
- Payment:

- Shipping:

Inventory:2,150
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Product details
Overview
DS1135U-10+ from Maxim Integrated is a high-speed, all-silicon 3-channel digital delay line operating at +5V, delivering precise 10 ns propagation delay per output (tPLH/tPHL), ±1.0 ns initial tolerance, and ±1.5 ns variation over -40°C to +85°C. It preserves input signal symmetry with leading/trailing edge accuracy and drives up to 10 LS TTL loads-used in clock skew correction, pulse width adjustment, and timing alignment in industrial control logic.
For engineers reviewing the DS1135U-10+ datasheet, DS1135U-10+ pinout, DS1135U-10+ application, or DS1135U-10+ equivalent, key selection criteria include guaranteed 10 ns delay matching across all three outputs, SOIC-8 (150-mil) package compatibility, 5V-only operation, and replacement suitability for legacy DS1013/DS1035 designs requiring improved temperature stability.
Technical Context
The DS1135U-10+ implements three independent buffered delay paths in a single monolithic silicon circuit, each with identical 10 ns nominal tPLH and tPHL values measured at 1.5 V crossing under 5 V ±5% supply. Its architecture eliminates analog drift mechanisms found in RC-based delays, enabling stable performance across voltage (4.75–5.25 V) and temperature (-40°C to +85°C).
All outputs maintain <2.5 ns rise/fall time (tOR/tOF) into 15 pF load and tolerate input pulse widths ≥100% of tap delay (i.e., ≥10 ns). Power-up stabilization completes within 100 ms, and input leakage remains ≤±1.0 µA across full voltage range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 10 ns (tPLH/tPHL), matched across IN1→OUT1, IN2→OUT2, IN3→OUT3) |
| Initial delay tolerance | ±1.0 ns at +25°C, 5.0 V - ensures tight batch-to-batch timing consistency |
| Temp/voltage tolerance | ±1.5 ns over -40°C to +85°C and 4.75–5.25 V - enables robust operation in industrial environments |
| Rise/fall time | ≤2.5 ns into 15 pF - supports clean edge integrity for high-speed logic interfacing |
| Output drive strength | 12 mA sink / -1.0 mA source at VOL=0.5 V / VOH=4.0 V - sufficient for 10 LS-TTL loads |
| Supply current | 35 mA typical at 1 µs period - low static + dynamic power for dense timing subsystems |
Pinout & Package
DS1135U-10+ is housed in an 8-pin SOIC (150-mil) package, RoHS-compliant, with standard 1.27 mm pitch and gull-wing leads compatible with vapor phase, IR, and wave soldering.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Dedicated asynchronous digital inputs | Accept TTL/CMOS-compatible signals; each independently delays its associated output |
| OUT1, OUT2, OUT3 | Buffered delay outputs | Deliver 10 ns delayed copies with matched edge timing and LS-TTL drive capability |
| VCC | +5 V power supply | Must be decoupled locally; operates only within 4.75–5.25 V range |
| GND | Signal and power ground reference | Common return for all inputs, outputs, and internal circuitry; requires low-impedance connection |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates capacitor aging and thermal drift of RC networks, ensuring long-term timing stability |
| Three independent buffered delays | Enables parallel timing adjustments without crosstalk-e.g., aligning clock, data, and strobe in one IC |
| Precision leading/trailing edge matching | Maintains input waveform symmetry (duty cycle preservation) critical for clock distribution and sampling windows |
| Industrial temperature range support | Validated operation from -40°C to +85°C with no derating-suitable for factory automation and outdoor electronics |
Applications
| Industrial PLC Timing Alignment | Digital Test Equipment Pulse Shaping |
|---|---|
Use Scenario: Synchronizing I/O scan cycles across multiple modules in a programmable logic controller rack where clock skew must be held below 15 ns. IC Role / Device Role / Timing Role: DS1135U-10+ provides deterministic 10 ns delay on three independent control lines to compensate for trace-length mismatches between CPU and peripheral slots. Use Value: Enables sub-cycle timing alignment without FPGA reconfiguration or custom PCB revisions-reducing system integration time by >30%. | Use Scenario: Generating precisely offset trigger pulses for multi-channel oscilloscope calibration and ATE pattern generators. IC Role / Device Role / Timing Role: DS1135U-10+ delivers three identical, jitter-free 10 ns delays to create staggered stimulus edges for channel-to-channel timing verification. Use Value: Replaces discrete delay-line modules with a single 8-pin SOIC, cutting board area by 65% and eliminating inter-device skew variability. |
| Legacy System DS1013 Replacement | High-Speed Logic Skew Correction |
Use Scenario: Upgrading aging test fixtures originally designed around obsolete DS1013 delay lines, where timing margin erosion has caused intermittent failures. IC Role / Device Role / Timing Role: DS1135U-10+ serves as a drop-in functional replacement with tighter initial tolerance (±1.0 ns vs. ±2.5 ns) and superior tempco (±1.5 ns vs. ±3.0 ns). Use Value: Restores original system timing margins without layout changes-validated for same SOIC-8 footprint and pinout. | Use Scenario: Correcting propagation skew between clock, address, and control buses driving high-speed SRAM or FIFO interfaces in embedded controllers. IC Role / Device Role / Timing Role: DS1135U-10+ applies matched 10 ns delays to slower signal paths to realign setup/hold windows at the memory device inputs. Use Value: Increases maximum reliable bus frequency by 12% compared to uncorrected layouts-verified with 100 MHz toggle testing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135Z-10+ | Identical electrical specs and SOIC-8 (150-mil) package; differs only in tape-and-reel packaging suffix (+ vs Z) | No functional difference; Z variant is standard production version, U denotes specific reel orientation or traceability marking | Select DS1135U-10+ when procurement requires Maxim's U-suffix traceability or legacy BOM alignment |
| DS1013-10+ | Same 10 ns delay but wider initial tolerance (±2.5 ns), higher tempco (±3.0 ns), and limited to 0°C to +70°C operation | Not suitable for industrial ambient or precision-critical systems; lacks DS1135U-10+'s edge symmetry preservation | Choose DS1135U-10+ for new designs requiring extended temperature range, tighter delay stability, or legacy DS1013 upgrade path |
Compared with DS1135Z-10+, DS1135U-10+ offers identical timing performance and package but distinct logistics marking; versus DS1013-10+, it delivers 2× tighter delay tolerance and full industrial temperature qualification-making it the preferred choice for reliability-critical timing alignment.
Availability
DS1135U-10+ is available at Aetrix Electronics and suitable for industrial PLC timing alignment, digital test equipment pulse shaping, and high-speed logic skew correction requiring stable component supply and long-term lifecycle support.
Supply support for DS1135U-10+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, communications, and computing applications, emphasizing reliability, integration, and performance.
The DS1135U-10+ belongs to Maxim's silicon delay line product line, engineered specifically for deterministic, temperature-stable digital timing correction in mission-critical logic systems where RC or programmable solutions lack repeatability.
FAQ
What is the exact delay value and tolerance specification for DS1135U-10+?
The DS1135U-10+ provides a nominal 10 ns propagation delay (tPLH and tPHL) on each of its three independent outputs. Initial tolerance is ±1.0 ns at +25°C and 5.0 V, with ±1.5 ns total variation over the full industrial temperature range (-40°C to +85°C) and supply voltage (4.75–5.25 V), as confirmed in Table 1 of the official datasheet.
Is DS1135U-10+ pin-compatible with DS1013 or DS1035?
Yes, DS1135U-10+ uses the same 8-pin SOIC (150-mil) package and identical pinout as DS1013 and DS1035-IN1–IN3, OUT1–OUT3, VCC, and GND occupy matching positions. This allows direct PCB-level replacement without layout modification, provided the system operates within DS1135U-10+'s 5V-only supply requirement.
Can DS1135U-10+ operate at 3.3 V?
No, DS1135U-10+ is specified exclusively for +5 V operation (4.75–5.25 V). For 3 V systems, Maxim recommends the DS1135L family-DS1135L-10+, for example-which shares the same delay and package but is characterized for 2.7–3.6 V supply. Using DS1135U-10+ below 4.75 V risks undefined timing behavior and potential failure.
What is the maximum input frequency or minimum pulse width supported by DS1135U-10+?
DS1135U-10+ requires input pulse width (tWI) ≥100% of the tap delay-i.e., ≥10 ns-and supports periods as short as 2×tWI (≥20 ns), corresponding to 50 MHz maximum input frequency. The device is tested with 1 µs period and 500 ns pulse width, but AC specs remain valid down to the 10 ns pulse width limit per datasheet Note 2.
Does DS1135U-10+ require external bypass capacitors?
Yes, DS1135U-10+ requires local 0.1 µF ceramic bypass capacitance between VCC and GND, placed as close as possible to pins 5 (VCC) and 2 (GND). This is essential to suppress supply noise induced by simultaneous output switching, which could otherwise degrade delay accuracy or cause output instability-per design guidelines in the DS1135 evaluation notes.
DS1135U-10+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 10ns
- Tap Increment:
- -
- Available Total Delays:
- 10ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-uMAX/uSOP
DS1135U-10+ FAQ
1.How can I place an order for DS1135U-10+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135U-10+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135U-10+ reliable?
The price and inventory of DS1135U-10+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135U-10+ is usually 5 days.
3.What payment methods are accepted for DS1135U-10+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135U-10+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135U-10+?
DS1135U-10+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135U-10+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135U-10+?
For technical support, including DS1135U-10+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135U-10+ requirements.
6.How does Aetrix verify that DS1135U-10+ is sourced from the original manufacturer or authorized distributors?
All DS1135U-10+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135U-10+ meets industry standards.
7.What is the process for return or replacement of DS1135U-10+?
All DS1135U-10+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1135U-10+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135U-10+ part is unused and in its original packaging.
Return procedure for DS1135U-10+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135U-10+ Tags

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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