Analog Devices Inc./Maxim Integrated DS1135U-25

Overview

DS1135U-25 from Maxim Integrated is a high-speed, all-silicon 3-channel digital delay line operating at +5V, delivering precise 25 ns propagation delay per output (tPLH/tPHL) with ±1.5 ns initial tolerance and ±2 ns tolerance over -40°C to +85°C. It features independent buffered outputs capable of driving 10 LS loads each, leading/trailing edge symmetry preservation, and SOIC-8 (150-mil) packaging. Used in clock skew management and timing alignment in high-speed logic systems.

For engineers reviewing the DS1135U-25 datasheet, DS1135U-25 pinout, DS1135U-25 application, or DS1135U-25 equivalent, key selection criteria include guaranteed 25 ns delay accuracy across temperature/voltage, 2.5 ns max output rise/fall time, 5V supply compatibility, industrial-grade operating range (-40°C to +85°C), and drop-in replacement capability for legacy DS1013/DS1035 designs.

Technical Context

The DS1135U-25 implements three independent, fully buffered delay paths within a single SOIC-8 package, each with identical 25 ns nominal propagation delay (tPLH = tPHL = 25 ns). Its all-silicon architecture eliminates quartz-based drift and enables stable performance across voltage (4.75V–5.25V) and temperature (-40°C to +85°C).

Each output maintains input waveform symmetry via matched leading and trailing edge delay accuracy, and supports TTL/LS logic interfacing with VIH ≥ 2.2 V, VIL ≤ 0.8 V, and 15 pF load capacitance. Power-up stabilization completes within 100 ms.

Key Specifications

Pinout & Package

DS1135U-25 is housed in an 8-pin SOIC (150-mil) package with standard JEDEC MS-012AC outline. Pin spacing is 1.27 mm, body width 3.9 mm, and total length 4.9 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar digital delay line applications.

Compared with DS1135Z-25+ and DS1035-25, the DS1135U-25 offers tighter delay tolerance (±1.5 ns vs. ±3 ns), faster edge transitions (2.5 ns vs. 4 ns), and lower active current (35 mA vs. 50 mA), making it optimal for high-density, thermally constrained, or high-fidelity timing applications.

Availability

DS1135U-25 is available at Aetrix Electronics and suitable for high-speed logic timing alignment, test equipment pulse delay calibration, and industrial PLC input signal conditioning requiring stable component supply and long-term obsolescence management.

Supply support for DS1135U-25 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, communications, and computing applications.

The DS1135 series was developed as a high-speed, silicon-based replacement for quartz and RC delay solutions, targeting applications needing deterministic, low-drift, multi-channel timing offsets in compact 5V systems.

FAQ

What is the guaranteed delay accuracy of DS1135U-25 over temperature and voltage?

The DS1135U-25 guarantees ±2 ns delay variation across the full industrial temperature range (-40°C to +85°C) and supply voltage range (4.75 V to 5.25 V). This includes both tPLH and tPHL measurements referenced to the 1.5 V switching threshold, ensuring matched rising and falling edge delays critical for duty-cycle preservation in the DS1135U-25.

Is DS1135U-25 pin-compatible with DS1013 or DS1035?

Yes, DS1135U-25 is a direct pin-compatible replacement for DS1013 and DS1035 in SOIC-8 packages. All share identical pin assignments (IN1–IN3, OUT1–OUT3, VCC, GND), same footprint, and compatible logic thresholds. The DS1135U-25 improves upon those predecessors with tighter delay tolerance, faster edges, and broader temperature qualification - no PCB changes required.

What load capacitance is specified for DS1135U-25 AC timing measurements?

DS1135U-25 AC electrical characteristics - including tPLH, tPHL, tOR, and tOF - are characterized with a 15 pF capacitive load on each output, representing the typical input capacitance of one 74F04 gate. Driving heavier loads will increase propagation delay and degrade edge rates, so layout should minimize trace capacitance to maintain DS1135U-25's specified 25 ns timing accuracy.

Does DS1135U-25 require external resistors or capacitors to operate?

No, DS1135U-25 is a fully self-contained delay line requiring only +5V supply and ground connections. No external timing components (resistors, capacitors, crystals) are needed. A 0.1 µF ceramic decoupling capacitor is recommended near the VCC pin, but no pull-ups, terminations, or bias networks are required for basic operation of the DS1135U-25.

What is the maximum input pulse frequency supported by DS1135U-25?

The DS1135U-25 supports input periods down to 2× the tap delay (i.e., minimum 50 ns period for 25 ns delay), corresponding to 20 MHz maximum fundamental frequency. Input pulse width must be ≥100% of tap delay (≥25 ns), and rise/fall times must be ≤3.0 ns (20%–80%) to ensure accurate delay measurement - verified under these conditions in the DS1135U-25 datasheet test setup.