Analog Devices Inc./Maxim Integrated DS1135Z-15+
- Part No.:
- DS1135Z-15+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135Z-15+.pdf
- Description:
- IC DELAY LINE 15NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:119
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Product details
Overview
DS1135Z-15+ from Maxim Integrated is a +5V, 3-channel all-silicon delay line with precise 15 ns per-output propagation delay (tPLH/tPHL), ±1.5 ns tolerance over -40°C to +85°C, and leading/trailing edge symmetry preservation for high-speed digital timing alignment in clock distribution and signal deskewing applications.
For engineers reviewing the DS1135Z-15+ datasheet, DS1135Z-15+ pinout, DS1135Z-15+ application, or DS1135Z-15+ equivalent, this device serves as a drop-in replacement for DS1013/DS1035 in industrial control, test equipment, and FPGA interface timing paths requiring stable, low-jitter, temperature-invariant delay with LS-TTL load drive capability.
Technical Context
The DS1135Z-15+ implements three independent buffered delay paths in a single 8-pin SOIC package, each delivering identical 15 ns nominal delay with matched tPLH and tPHL characteristics. Its all-silicon architecture eliminates quartz aging and thermal hysteresis, while internal logic buffering ensures consistent edge fidelity across temperature and supply voltage variations (4.75 V–5.25 V).
Each output drives up to 10 LS-TTL loads with 2.0–2.5 ns rise/fall times and maintains input pulse width integrity-critical for synchronous data capture and setup/hold margin optimization in high-speed digital systems where deterministic latency is mandatory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 15 ns ±1.5 ns over -40°C to +85°C - guarantees deterministic latency for timing-critical signal alignment |
| Supply voltage | +5 V ±5% (4.75 V–5.25 V) - compatible with standard TTL/CMOS logic rails |
| Rise/fall time | 2.0–2.5 ns - supports >200 MHz signal edges without distortion |
| Output drive | 10 LS-TTL loads - enables fanout without external buffers in dense logic interfaces |
| Input capacitance | 10 pF - minimizes loading on upstream drivers and preserves signal integrity |
| Power-up time | 100 ms - defines minimum stabilization delay before valid delay operation begins |
Pinout & Package
DS1135Z-15+ is housed in an 8-pin SOIC (150-mil) package with gull-wing leads, RoHS-compliant, and qualified for vapor phase, IR, and wave soldering.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Digital input signals | Three independent TTL/CMOS-compatible inputs accepting 0.8 V/2.2 V thresholds |
| OUT1, OUT2, OUT3 | Buffered delayed outputs | Three matched 15 ns-delayed outputs, each capable of driving 10 LS loads |
| VCC | Positive supply | +5 V power rail; decoupling required at pin for noise-sensitive timing stability |
| GND | Ground reference | Common return path for all inputs, outputs, and internal circuitry |
Key Features
| Feature | Design Value |
|---|---|
| Precise leading & trailing edge delay | tPLH and tPHL both 15 ns ±1.5 ns - preserves input duty cycle and enables accurate skew correction |
| All-silicon construction | No quartz resonator or MEMS element - eliminates aging, shock sensitivity, and thermal hysteresis |
| Temperature-stable delay | ±1.5 ns variation over -40°C to +85°C - ensures consistent timing in industrial environments |
| LS-TTL load compatibility | Each output drives 10 LS loads - reduces need for external level-shifting or buffering stages |
Applications
| Test Equipment Signal Deskewing | FPGA I/O Timing Alignment |
|---|---|
Use Scenario: Synchronizing multiple acquisition channels in automated test equipment where input signal arrival times vary due to trace length mismatches. IC Role / Device Role / Timing Role: DS1135Z-15+ provides calibrated, matched delays on three independent channels to equalize path latency before digitization. Use Value: Enables sub-nanosecond channel-to-channel skew correction without custom PCB routing or discrete delay networks. | Use Scenario: Aligning parallel data bus signals between FPGA I/O banks and external memory or ADC interfaces operating at >100 MHz. IC Role / Device Role / Timing Role: DS1135Z-15+ inserts deterministic 15 ns delay on selected data or strobe lines to meet setup/hold windows. Use Value: Eliminates timing closure issues caused by inter-bank routing asymmetry while maintaining full-speed operation. |
| Industrial PLC Clock Distribution | Digital Logic Skew Compensation |
Use Scenario: Distributing synchronized clock edges to multiple isolated I/O modules in programmable logic controllers under wide ambient temperature swings. IC Role / Device Role / Timing Role: DS1135Z-15+ acts as a temperature-invariant delay node in clock tree branches to compensate for propagation differences. Use Value: Maintains <±2 ns skew across -40°C to +85°C, ensuring deterministic real-time control loop execution. | Use Scenario: Correcting timing mismatches between parallel control signals in legacy TTL-based industrial controllers. IC Role / Device Role / Timing Role: DS1135Z-15+ replaces aging DS1013/DS1035 units with identical pinout and improved delay stability. Use Value: Restores reliable system timing without board redesign or firmware changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-channel silicon delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135Z-12+ | 12 ns fixed delay per output; ±1.0 ns initial tolerance | Suitable where shorter latency is acceptable and tighter initial accuracy is prioritized | Select when 3 ns less delay meets system timing budget and tighter room-temperature spec is required |
| DS1135Z-20+ | 20 ns fixed delay per output; ±1.5 ns tolerance over -40°C to +85°C | Better suited for longer-path deskewing or wider setup margin requirements | Choose when additional delay headroom is needed for future design iterations or higher-voltage margin scenarios |
Compared with DS1135Z-12+ and DS1135Z-20+, the DS1135Z-15+ offers the optimal balance of moderate delay depth, industrial-grade temperature stability, and proven drop-in compatibility with legacy DS1013/DS1035 designs-making it ideal for mid-range timing correction in production systems.
Availability
DS1135Z-15+ is available at Aetrix Electronics and suitable for industrial automation, test instrumentation, and FPGA-based embedded systems requiring stable component supply with guaranteed long-term availability and RoHS-compliant packaging.
Supply support for DS1135Z-15+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, automotive, and communications applications.
The DS1135 series was developed as a high-speed, all-silicon replacement for legacy quartz-based and discrete delay solutions-targeting applications demanding repeatable, maintenance-free timing alignment without crystal aging or mechanical fragility.
FAQ
What is the guaranteed delay accuracy of DS1135Z-15+ over its full operating temperature range?
The DS1135Z-15+ guarantees ±1.5 ns delay tolerance over -40°C to +85°C for both tPLH and tPHL. This specification is measured under VCC = 4.75 V–5.25 V and reflects total variation including initial offset, temperature drift, and supply sensitivity-ensuring predictable latency in harsh industrial environments where the DS1135Z-15+ is commonly deployed.
Is DS1135Z-15+ pin-compatible with DS1013 or DS1035?
Yes, DS1135Z-15+ is a direct pin-compatible replacement for DS1013 and DS1035 in the same 8-pin SOIC package. The pin assignment (IN1–IN3, OUT1–OUT3, VCC, GND), footprint, and electrical interface are identical-enabling drop-in upgrades without PCB modification. DS1135Z-15+ improves upon those predecessors with tighter delay tolerance and enhanced temperature stability.
Can DS1135Z-15+ operate from a 3.3 V supply?
No, DS1135Z-15+ is specified only for +5 V operation (4.75 V–5.25 V). For 3 V applications, Maxim recommends the DS1135L family-distinct devices with different internal design and voltage rating. Using DS1135Z-15+ below 4.75 V may result in undefined delay behavior, increased jitter, or failure to meet AC specifications.
What is the maximum capacitive load DS1135Z-15+ can drive while maintaining specified delay and edge performance?
The DS1135Z-15+ is characterized to drive up to 10 LS-TTL loads (equivalent to ~15 pF total load capacitance) while maintaining its 15 ns delay accuracy and 2.0–2.5 ns rise/fall times. Exceeding this load increases propagation delay variation and degrades edge fidelity-so proper termination and load matching are essential when using DS1135Z-15+ in high-fanout configurations.
Does DS1135Z-15+ require external decoupling capacitors?
Yes, DS1135Z-15+ requires a 0.1 µF ceramic decoupling capacitor placed as close as possible to the VCC pin. This is critical to suppress supply-induced jitter and maintain delay stability-especially under fast-switching conditions. The DS1135Z-15+ datasheet specifies that inadequate decoupling directly impacts tPLH/tPHL repeatability and may cause timing violations in systems relying on precise latency.
DS1135Z-15+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 15ns
- Tap Increment:
- -
- Available Total Delays:
- 15ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135Z-15+ FAQ
1.How can I place an order for DS1135Z-15+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135Z-15+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135Z-15+ reliable?
The price and inventory of DS1135Z-15+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135Z-15+ is usually 5 days.
3.What payment methods are accepted for DS1135Z-15+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135Z-15+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135Z-15+?
DS1135Z-15+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135Z-15+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135Z-15+?
For technical support, including DS1135Z-15+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135Z-15+ requirements.
6.How does Aetrix verify that DS1135Z-15+ is sourced from the original manufacturer or authorized distributors?
All DS1135Z-15+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135Z-15+ meets industry standards.
7.What is the process for return or replacement of DS1135Z-15+?
All DS1135Z-15+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1135Z-15+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135Z-15+ part is unused and in its original packaging.
Return procedure for DS1135Z-15+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135Z-15+ Tags

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Analog Devices Inc.

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