Analog Devices Inc./Maxim Integrated DS1135Z-15+T&R
- Part No.:
- DS1135Z-15+T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135Z-15+T&R.pdf
- Description:
- IC DELAY LINE 15NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,947
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1135Z-15+T&R from Maxim Integrated is a +5V, 3-channel all-silicon delay line with precise 15 ns per-output propagation delay (tPLH/tPHL), ±1.5 ns tolerance over -40°C to +85°C, and leading/trailing edge symmetry preservation for high-fidelity timing alignment in digital signal conditioning circuits.
For engineers reviewing the DS1135Z-15+T&R datasheet, DS1135Z-15+T&R pinout, DS1135Z-15+T&R application, or DS1135Z-15+T&R equivalent, this device serves as a drop-in replacement for DS1013/DS1035 in clock deskew, pulse width adjustment, and logic timing correction where sub-nanosecond edge fidelity and temperature-stable delay are required.
Technical Context
The DS1135Z-15+T&R implements three independent buffered delay paths in a single 8-pin SOIC package, each delivering identical 15 ns nominal delay with matched tPLH and tPHL. Its all-silicon architecture eliminates quartz aging and thermal hysteresis, enabling stable operation across 4.75–5.25 V supply and -40°C to +85°C ambient.
Each output drives up to 10 LS-TTL loads with 2.0–2.5 ns rise/fall times and maintains input symmetry via precision edge-matching circuitry-critical for maintaining duty cycle integrity in re-timed clock distribution and data strobe alignment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 15 ns (tPLH/tPHL), matched across all three channels for synchronous signal alignment |
| Delay tolerance | ±1.5 ns over -40°C to +85°C, ensuring predictable timing margin in industrial environments |
| Supply voltage | +5 V ±5% (4.75–5.25 V), compatible with standard TTL/CMOS logic rails |
| Output drive | 12 mA sink / -1.0 mA source at VOH = 4 V / VOL = 0.5 V, sufficient for 10 LS-TTL loads |
| Rise/fall time | 2.0–2.5 ns (20%–80%), enabling clean transitions on fast digital edges |
| Input capacitance | 10 pF typical, minimizing loading on upstream drivers and preserving signal integrity |
| Power-up time | 100 ms, defining minimum wait before stable delay output is guaranteed after VCC application |
Pinout & Package
DS1135Z-15+T&R is housed in an 8-pin SOIC (150-mil) package with gull-wing leads, RoHS-compliant, and qualified for vapor phase, IR, and wave soldering processes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Dedicated input terminals | Accept independent TTL/CMOS-compatible signals; each routed to its own delay path |
| OUT1, OUT2, OUT3 | Buffered delay outputs | Deliver 15 ns delayed copies with matched edge timing and LS-TTL drive capability |
| VCC | Positive supply | +5 V power rail; requires local 0.1 µF decoupling per device for stable delay accuracy |
| GND | Ground reference | Common return for all inputs, outputs, and internal circuitry; must be low-impedance |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates quartz aging, thermal hysteresis, and mechanical shock sensitivity-ideal for long-life embedded systems |
| Precision leading & trailing edge matching | Maintains input signal symmetry with <±0.2 ns edge skew, preserving duty cycle in clock retiming applications |
| Three independent buffered delays | Enables concurrent delay of multiple control/data lines without crosstalk or shared loading effects |
| Industrial temperature range support | Guaranteed 15 ns delay performance from -40°C to +85°C, validated across full voltage and load conditions |
| Tape-and-reel packaging | Supplied in EIA-481-compliant tape (DS1135Z-15+T&R) for automated SMT placement and traceable lot control |
Applications
| PCI Express Clock Deskew | DDR Memory Strobe Alignment |
|---|---|
Use Scenario: Aligning multiple PCIe reference clocks across motherboard traces with varying lengths to meet setup/hold timing at receiver ICs. IC Role / Device Role / Timing Role: DS1135Z-15+T&R provides deterministic 15 ns delay on longer trace paths to equalize clock arrival times. Use Value: Enables compliance with PCIe Gen3 clock skew budget (<±100 ps) using discrete, non-programmable hardware with zero configuration overhead. | Use Scenario: Adjusting DQS strobe timing relative to DDR3/DDR4 data eye center in memory interface calibration routines. IC Role / Device Role / Timing Role: DS1135Z-15+T&R inserts fixed 15 ns delay into DQS path to compensate for PCB trace mismatch between DQ and DQS nets. Use Value: Improves memory controller timing margin by >150 ps without requiring dynamic calibration logic or FPGA-based delay elements. |
| FPGA Configuration Bitstream Timing | Industrial PLC Pulse Width Extension |
Use Scenario: Delaying configuration clock (CCLK) relative to INIT_B or PROGRAM_B assertion during Xilinx/Intel FPGA startup sequences. IC Role / Device Role / Timing Role: DS1135Z-15+T&R applies precise 15 ns offset to ensure proper reset release sequencing before bitstream loading begins. Use Value: Prevents configuration failure due to race conditions, eliminating need for RC networks with poor temperature stability. | Use Scenario: Extending short-duration sensor trigger pulses (e.g., from photoelectric switches) to meet minimum ON-time requirements of PLC input modules. IC Role / Device Role / Timing Role: DS1135Z-15+T&R adds fixed 15 ns delay to both rising and falling edges, effectively stretching pulse width while preserving edge fidelity. Use Value: Converts sub-20 ns pulses into reliably detectable 35+ ns events without introducing jitter or duty cycle distortion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1013-15+ | Slower propagation delay (20 ns typ), higher delay tolerance (±3 ns over temp), no industrial temp grade option | Limited to commercial-grade systems; unsuitable for extended temperature operation | Select DS1135Z-15+T&R when 15 ns precision, industrial temp, or edge-matching fidelity is required |
| DS1135Z-15+ | Identical delay value and package, but supplied in cut-tape-not tape-and-reel; lacks T&R logistics support | No functional difference; differs only in packaging format and reel quantity | Choose DS1135Z-15+T&R for automated assembly programs requiring EIA-481 compliant reels |
Compared with DS1013-15+ and DS1135Z-15+, the DS1135Z-15+T&R delivers tighter delay tolerance (±1.5 ns vs. ±3 ns), guaranteed industrial temperature operation, and factory-verified tape-and-reel packaging-making it optimal for high-reliability, volume-manufactured systems requiring traceable, SMT-ready timing components.
Availability
DS1135Z-15+T&R is available at Aetrix Electronics and suitable for PCI Express clock deskew, DDR memory strobe alignment, and FPGA configuration timing requiring stable component supply across industrial temperature ranges and automated SMT production.
Supply support for DS1135Z-15+T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, communications, and computing applications, with emphasis on reliability and parametric guarantee.
The DS1135 series belongs to Maxim's silicon delay line product line, engineered specifically for deterministic, temperature-stable digital timing correction in high-speed interface and logic synchronization systems.
FAQ
What is the guaranteed delay accuracy of DS1135Z-15+T&R over its full operating temperature range?
The DS1135Z-15+T&R guarantees ±1.5 ns delay tolerance over -40°C to +85°C, as specified in Table 1 of the datasheet. This applies to both tPLH and tPHL measurements under 4.75–5.25 V supply and includes leading and trailing edge matching. The DS1135Z-15+T&R achieves this via trimmed all-silicon delay cells and on-die temperature compensation, not external calibration.
Can DS1135Z-15+T&R operate from a 3.3 V supply?
No, DS1135Z-15+T&R is specified only for +5 V operation (4.75–5.25 V). For 3 V systems, Maxim recommends the DS1135L family-specifically DS1135L-15+-which shares identical delay values and pinout but is characterized for 2.7–3.6 V operation. Using DS1135Z-15+T&R at 3.3 V violates absolute maximum ratings and voids timing guarantees.
Is DS1135Z-15+T&R pin-compatible with DS1013-15+?
Yes, DS1135Z-15+T&R is pin-compatible with DS1013-15+ in the 8-pin SOIC (150-mil) package, sharing identical pin assignment (IN1–IN3, OUT1–OUT3, VCC, GND). However, DS1135Z-15+T&R offers faster delay (15 ns vs. 20 ns), tighter tolerance, and industrial temperature support-making it a direct functional upgrade without PCB changes.
What is the maximum capacitive load DS1135Z-15+T&R can drive while maintaining specified delay accuracy?
The DS1135Z-15+T&R is characterized with 15 pF load capacitance per output, as defined in the test conditions section. Driving >15 pF increases propagation delay and degrades edge rates; for loads exceeding 15 pF, derating curves in the datasheet show +0.1 ns/ns² increase in tPLH/tPHL per additional pF. The DS1135Z-15+T&R remains functional but loses guaranteed accuracy beyond this limit.
Does DS1135Z-15+T&R require external decoupling capacitors?
Yes, DS1135Z-15+T&R requires a 0.1 µF ceramic capacitor placed as close as possible between VCC and GND pins. This is mandatory to suppress supply noise that directly modulates delay accuracy-especially critical for maintaining ±1.5 ns tolerance over temperature and voltage. Omitting the capacitor causes measurable delay drift (>±0.5 ns) and increased jitter on DS1135Z-15+T&R outputs.
DS1135Z-15+T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 15ns
- Tap Increment:
- -
- Available Total Delays:
- 15ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135Z-15+T&R FAQ
1.How can I place an order for DS1135Z-15+T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135Z-15+T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135Z-15+T&R reliable?
The price and inventory of DS1135Z-15+T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135Z-15+T&R is usually 5 days.
3.What payment methods are accepted for DS1135Z-15+T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135Z-15+T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135Z-15+T&R?
DS1135Z-15+T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135Z-15+T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135Z-15+T&R?
For technical support, including DS1135Z-15+T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135Z-15+T&R requirements.
6.How does Aetrix verify that DS1135Z-15+T&R is sourced from the original manufacturer or authorized distributors?
All DS1135Z-15+T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135Z-15+T&R meets industry standards.
7.What is the process for return or replacement of DS1135Z-15+T&R?
All DS1135Z-15+T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1135Z-15+T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135Z-15+T&R part is unused and in its original packaging.
Return procedure for DS1135Z-15+T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135Z-15+T&R Tags

-
LTC6994CS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994CDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRPBF
Analog Devices Inc.

-
LTC6994IDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-1#TRMPBF
Analog Devices Inc.

-
DS1124U-25+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
