Analog Devices Inc./Maxim Integrated DS1135Z-6/T&R
- Part No.:
- DS1135Z-6/T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135Z-6/T&R.pdf
- Description:
- IC DELAY LINE 6NS 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1135Z-6/T&R from Maxim Integrated is a high-speed, all-silicon 3-channel logic delay line operating at +5V with identical 6ns nominal delay per output (tPLH/tPHL), ±1.0ns initial tolerance, and ±1.5ns tolerance over -40°C to +85°C. It preserves input signal symmetry with precise leading/trailing edge accuracy and drives up to 10 LS loads. Used in high-speed digital timing alignment for FPGA clock deskew and test instrumentation.
For engineers reviewing the DS1135Z-6/T&R datasheet, DS1135Z-6/T&R pinout, DS1135Z-6/T&R application, or DS1135Z-6/T&R equivalent, key selection criteria include guaranteed 6ns delay matching across three outputs, industrial temperature support (-40°C to +85°C), SOIC-8 (150-mil) package compatibility, and replacement suitability for legacy DS1013/DS1035 designs.
Technical Context
The DS1135Z-6/T&R implements three independent buffered delay paths in a single monolithic silicon circuit, each delivering matched 6ns propagation delay (tPLH = tPHL = 6ns) with sub-nanosecond edge precision. Its architecture eliminates analog drift mechanisms found in RC-based delay lines.
It operates strictly at +5V (4.75V–5.25V), supports 100% tap delay input pulse width, and features 2.0–2.5ns output rise/fall times (tOR/tOF) under 15pF load. Power-up stabilization completes within 100ms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 6ns (tPLH/tPHL), matched across all three channels for synchronous signal alignment |
| Initial delay tolerance | ±1.0ns at +25°C and VCC = 5.0V - enables tight setup/hold margin control |
| Tolerance over temp/volt | ±1.5ns from -40°C to +85°C and 4.75V–5.25V - ensures stable timing in industrial environments |
| Output drive strength | Drives ≥10 LS-TTL loads - sufficient for fanout without external buffers |
| Rise/fall time | 2.0–2.5ns (1.5V transition, 15pF load) - maintains signal integrity in >100MHz digital systems |
| Supply voltage | +5V ±5% (4.75V–5.25V) - compatible with standard 5V logic rails and decoupling practices |
| Power-up time | 100ms - defines minimum reset-to-operational latency after power application |
Pinout & Package
DS1135Z-6/T&R is housed in an 8-pin SOIC (150-mil) package, RoHS-compliant, vapor-phase, IR, and wave solderable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Dedicated logic inputs | Accept TTL/CMOS-compatible signals; each independently delays its input to corresponding output |
| OUT1, OUT2, OUT3 | Buffered delay outputs | Deliver 6ns-delayed, edge-accurate copies of respective inputs; each drives ≥10 LS loads |
| VCC | Positive supply | +5V power rail; requires local 0.1µF ceramic decoupling per device |
| GND | Ground reference | Common return for all inputs, outputs, and internal circuitry; must be low-impedance |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates aging, temperature hysteresis, and voltage drift inherent in RC or analog delay solutions |
| Precision leading & trailing edge delay | Preserves input duty cycle symmetry - critical for clock deskew and pulse-width-sensitive logic |
| Three independent buffered delays | Enables parallel timing adjustment of multiple signal paths without cross-talk or loading interaction |
| Industrial temperature range support | Validated operation from -40°C to +85°C - suitable for embedded control and test equipment |
Applications
| High-Speed FPGA Clock Deskew | Automated Test Equipment (ATE) Signal Alignment |
|---|---|
Use Scenario: Aligning multiple clock domains across FPGA I/O banks to meet setup/hold timing closure. IC Role / Device Role / Timing Role: DS1135Z-6/T&R provides matched 6ns delay on three independent clock paths to compensate for PCB trace skew. Use Value: Enables deterministic phase alignment without custom layout tuning or programmable delay IC overhead. | Use Scenario: Synchronizing stimulus and capture channels in high-speed digital pattern generators. IC Role / Device Role / Timing Role: DS1135Z-6/T&R delivers identical 6ns delay to three parallel data strobes, ensuring simultaneous sampling windows. Use Value: Reduces channel-to-channel timing jitter to <1.5ns over temperature, improving test repeatability. |
| Digital Logic Glitch Filtering | Legacy System Timing Upgrade |
Use Scenario: Suppressing narrow asynchronous glitches on control lines before entering synchronous state machines. IC Role / Device Role / Timing Role: DS1135Z-6/T&R acts as a fixed 6ns pulse-width filter by delaying both edges equally to reject sub-6ns transients. Use Value: Provides deterministic noise immunity without adding propagation uncertainty from retriggerable monostables. | Use Scenario: Replacing obsolete DS1013/DS1035 delay lines in field-deployed industrial controllers. IC Role / Device Role / Timing Role: DS1135Z-6/T&R serves as a drop-in +5V-compatible upgrade with improved delay stability and edge fidelity. Use Value: Extends product lifecycle without PCB redesign, leveraging identical SOIC-8 footprint and pinout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135Z-8/T&R | 8ns nominal delay per output; same tolerance, package, and drive capability | Suitable where longer, but still matched, delay is required for timing margin expansion | Select when system-level timing analysis requires 8ns instead of 6ns alignment offset |
| DS1135Z-10/T&R | 10ns nominal delay per output; identical AC/DC specs and thermal performance | Used in applications needing greater inter-signal separation, e.g., wider clock/data window spacing | Choose for designs requiring increased setup/hold guardband without changing board layout |
Compared with DS1135Z-8/T&R and DS1135Z-10/T&R, the DS1135Z-6/T&R offers the shortest matched delay while retaining identical industrial temperature stability, edge precision, and SOIC-8 compatibility - making it optimal for minimal-latency synchronous alignment.
Availability
DS1135Z-6/T&R is available at Aetrix Electronics and suitable for high-speed digital test instrumentation, FPGA-based embedded controllers, and industrial timing upgrade programs requiring stable component supply and long-term obsolescence mitigation.
Supply support for DS1135Z-6/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, communications, and computing applications.
The DS1135 series was developed as a high-speed, all-silicon replacement for legacy delay lines, targeting applications demanding matched multi-channel delay with nanosecond edge fidelity and industrial reliability.
FAQ
What is the exact delay value and tolerance specification for DS1135Z-6/T&R?
The DS1135Z-6/T&R delivers a nominal 6ns delay on each of its three outputs (tPLH and tPHL), with ±1.0ns initial tolerance at +25°C and VCC = 5.0V. Over the full industrial temperature range (-40°C to +85°C) and supply voltage (4.75V–5.25V), delay tolerance is ±1.5ns - guaranteed per device, not typical.
Is DS1135Z-6/T&R pin-compatible with DS1013 or DS1035?
Yes, DS1135Z-6/T&R uses the same 8-pin SOIC (150-mil) package and identical pinout (IN1–IN3, OUT1–OUT3, VCC, GND) as DS1013 and DS1035. It is explicitly recommended as a direct replacement, requiring no PCB changes when upgrading legacy designs.
Does DS1135Z-6/T&R support 3.3V operation?
No, DS1135Z-6/T&R is specified only for +5V operation (4.75V–5.25V). For 3V-compatible alternatives, refer to the DS1135L family - DS1135Z-6/T&R will not function reliably below 4.75V and is not characterized for 3.3V use.
What is the maximum capacitive load the outputs of DS1135Z-6/T&R can drive?
DS1135Z-6/T&R outputs are characterized to drive up to 10 LS-TTL loads, equivalent to ~15pF total load capacitance with 2.0–2.5ns rise/fall times. Driving heavier loads may degrade edge fidelity and delay accuracy; external buffering is recommended beyond this limit.
How does DS1135Z-6/T&R preserve input signal symmetry?
DS1135Z-6/T&R achieves leading and trailing edge precision by using matched internal delay paths for both rising and falling transitions. This ensures tPLH and tPHL are equal (6ns each), maintaining input duty cycle and minimizing jitter - a feature confirmed in the datasheet's "Leading and Trailing Edge Precision" specification.
DS1135Z-6/T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 6ns
- Tap Increment:
- -
- Available Total Delays:
- 6ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135Z-6/T&R FAQ
1.How can I place an order for DS1135Z-6/T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135Z-6/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135Z-6/T&R reliable?
The price and inventory of DS1135Z-6/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135Z-6/T&R is usually 5 days.
3.What payment methods are accepted for DS1135Z-6/T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135Z-6/T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135Z-6/T&R?
DS1135Z-6/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135Z-6/T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135Z-6/T&R?
For technical support, including DS1135Z-6/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135Z-6/T&R requirements.
6.How does Aetrix verify that DS1135Z-6/T&R is sourced from the original manufacturer or authorized distributors?
All DS1135Z-6/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135Z-6/T&R meets industry standards.
7.What is the process for return or replacement of DS1135Z-6/T&R?
All DS1135Z-6/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1135Z-6/T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135Z-6/T&R part is unused and in its original packaging.
Return procedure for DS1135Z-6/T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135Z-6/T&R Tags

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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