Analog Devices Inc./Maxim Integrated DS1135Z-8/T&R
- Part No.:
- DS1135Z-8/T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135Z-8/T&R.pdf
- Description:
- IC DELAY LINE 8NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,713
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1135Z-8/T&R from Maxim Integrated is a high-speed, all-silicon 3-channel digital delay line operating at +5V, delivering precise 8 ns propagation delay per output (tPLH/tPHL) with ±1.0 ns initial tolerance and ±1.5 ns tolerance over -40°C to +85°C. It features independent buffered outputs capable of driving 10 LS loads, leading/trailing edge symmetry preservation, and SOIC-8 (150-mil) packaging for industrial timing control applications.
For engineers reviewing the DS1135Z-8/T&R datasheet, DS1135Z-8/T&R pinout, DS1135Z-8/T&R application, or DS1135Z-8/T&R equivalent, this page provides verified timing accuracy, thermal/voltage stability data, SOIC-8 terminal mapping, and direct replacement guidance for legacy DS1013/DS1035 designs requiring sub-nanosecond edge fidelity and 5V-compatible logic interfacing.
Technical Context
The DS1135Z-8/T&R implements three independent, fully buffered delay paths in a single monolithic silicon IC-no external RC networks or crystal-based elements. Each channel delivers matched 8 ns nominal delay (tPLH = tPHL) with identical leading and trailing edge precision, preserving input signal symmetry across temperature and supply voltage variation (4.75 V–5.25 V).
It operates as a deterministic, zero-jitter propagation delay element-not a programmable oscillator or PLL-based timing generator. Its logic-level compatibility (VIH ≥ 2.2 V, VIL ≤ 0.8 V), fast 2.0–2.5 ns rise/fall times, and 100 ms power-up stabilization time define its role in high-fidelity digital signal alignment within synchronous bus interfaces and clock domain crossing circuits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 8 ns (tPLH/tPHL), matched across all three channels for synchronized signal skew correction |
| Initial delay tolerance | ±1.0 ns at +25°C, 5.0 V - enables tight setup/hold margin control without calibration |
| Tolerance over temp/volt | ±1.5 ns (-40°C to +85°C, 4.75–5.25 V) - ensures stable timing in industrial environments |
| Output drive strength | 12 mA sink / -1.0 mA source at VOH=4.0 V/VOL=0.5 V - supports direct 74F04-equivalent loading |
| Rise/fall time | 2.0–2.5 ns - maintains signal integrity for >200 MHz edge rates in high-speed logic |
| Supply voltage | +5 V ±5% (4.75–5.25 V) - compatible with standard TTL/CMOS 5V systems |
| Power-up time | 100 ms - defines minimum reset-to-operational latency after VCC ramp |
Pinout & Package
DS1135Z-8/T&R is housed in an 8-pin SOIC package (150-mil width, outline 21-0041), RoHS-compliant, vapor-phase, IR, and wave solderable. Pin 1 is located at the top-left corner adjacent to the notch or dot marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | IN2 | Second independent input channel - accepts standard 5V logic signals for dedicated 8 ns delay path |
| 2 | GND | Digital ground reference - must be low-impedance connection to minimize delay jitter and crosstalk |
| 3 | IN3 | Third independent input channel - enables parallel triple-delay operation without external fanout |
| 4 | IN1 | Primary input channel - initiates first 8 ns delay path; pin position optimized for minimal trace length in layout |
| 5 | VCC | +5 V supply - requires local 0.1 µF ceramic decoupling per device to maintain delay stability |
| 6 | OUT1 | Buffered output for IN1 - delivers full-swing 5V logic with preserved edge symmetry and load drive capability |
| 7 | OUT2 | Buffered output for IN2 - electrically isolated from OUT1/OUT3 to prevent inter-channel coupling |
| 8 | OUT3 | Buffered output for IN3 - completes triple-output timing alignment with matched propagation characteristics |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates aging, drift, and environmental sensitivity inherent in RC or crystal-based delay solutions |
| Three independent buffered delays | Enables concurrent skew correction across three signal paths without external buffering or fanout gates |
| Precision leading/trailing edge matching | Maintains 50% duty cycle fidelity at output - critical for clock distribution and synchronous sampling |
| Stable over temperature and voltage | ±1.5 ns max deviation across full industrial range ensures predictable timing in harsh environments |
| SOIC-8 tape-and-reel packaging | Supports automated SMT assembly with industry-standard 8 mm carrier tape (EIA-481 compliant) |
Applications
| PCI Express Timing Alignment | Industrial PLC I/O Synchronization |
|---|---|
Use Scenario: Aligning multiple PCIe Gen1/Gen2 reference clock signals to meet skew budget requirements across backplane traces. IC Role / Device Role / Timing Role: DS1135Z-8/T&R provides deterministic 8 ns delay on individual clock lanes to compensate for unequal PCB trace lengths. Use Value: Enables compliance with PCIe 2.5 GT/s timing specs by reducing inter-lane skew to <100 ps without active PLL re-timing. | Use Scenario: Synchronizing digital input sampling across distributed I/O modules in modular PLC chassis with mixed cable lengths. IC Role / Device Role / Timing Role: DS1135Z-8/T&R applies matched delay to sensor input channels before ADC sampling to eliminate phase misalignment. Use Value: Improves effective resolution of multi-channel analog acquisition by ensuring simultaneous sampling window alignment across modules. |
| Test Equipment Signal Staging | Legacy Bus Skew Compensation |
Use Scenario: Generating precisely staggered trigger pulses for multi-channel oscilloscope or logic analyzer capture windows. IC Role / Device Role / Timing Role: DS1135Z-8/T&R delivers three independent, identically delayed outputs from a common trigger source. Use Value: Allows sub-nanosecond temporal resolution between instrument channels without FPGA-based delay generation. | Use Scenario: Correcting propagation delay mismatches in legacy ISA or VMEbus address/data strobes caused by board-level routing differences. IC Role / Device Role / Timing Role: DS1135Z-8/T&R inserts calibrated 8 ns delay on faster signal paths to equalize total path latency. Use Value: Restores timing margins for 8/16-bit synchronous bus protocols operating up to 10 MHz without redesigning backplane layout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135Z-8+ | Same die, identical 8 ns delay and SOIC-8 package; "+" suffix denotes RoHS-compliant lead finish (vs. "/T&R" tape-and-reel packaging) | No functional difference - only packaging format differs (bulk vs. tape-and-reel); both support same thermal and electrical performance | Select DS1135Z-8/T&R for automated SMT production; choose DS1135Z-8+ for hand-solder prototyping or small-batch builds |
| DS1013-8 | Legacy bipolar implementation; higher ICC (50 mA), slower rise/fall (>4 ns), wider delay tolerance (±3 ns over temp), DIP-14 or SOIC-14 packaging | Larger footprint, higher power, lower precision - suitable only where legacy form factor or cost constraints override timing fidelity needs | DS1135Z-8/T&R offers superior edge fidelity and thermal stability but requires SOIC-8 layout; not pin-compatible with DS1013-8 |
Compared with DS1135Z-8+ and DS1013-8, the DS1135Z-8/T&R delivers best-in-class 8 ns delay accuracy and edge symmetry in a compact, production-ready tape-and-reel format-making it optimal for new industrial and test equipment designs demanding repeatable sub-nanosecond timing alignment.
Availability
DS1135Z-8/T&R is available at Aetrix Electronics and suitable for PCI Express timing alignment, industrial PLC I/O synchronization, test equipment signal staging, and legacy bus skew compensation requiring stable component supply across extended temperature ranges and high-volume manufacturing cycles.
Supply support for DS1135Z-8/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, communications, and computing applications, with emphasis on reliability, integration, and performance under stress.
The DS1135 series belongs to Maxim's high-speed timing portfolio, engineered specifically for deterministic digital signal delay correction in mission-critical industrial and test instrumentation systems where RC or crystal-based alternatives introduce unacceptable drift or jitter.
FAQ
What is the guaranteed delay accuracy of DS1135Z-8/T&R over its full operating temperature range?
The DS1135Z-8/T&R guarantees ±1.5 ns delay tolerance (tPLH/tPHL) across -40°C to +85°C at VCC = 4.75 V to 5.25 V. This specification covers both leading and trailing edges and is measured at the 1.5 V switching threshold. Initial tolerance at +25°C is tighter at ±1.0 ns, enabling precise timing margin allocation during system design. The DS1135Z-8/T&R achieves this stability via all-silicon delay architecture with no external components required.
Can DS1135Z-8/T&R replace DS1013 or DS1035 in existing designs without layout changes?
No, DS1135Z-8/T&R cannot be used as a drop-in replacement for DS1013 or DS1035 due to differing packages and pin counts: DS1135Z-8/T&R uses an 8-pin SOIC, while DS1013 and DS1035 are offered in 14-pin DIP or SOIC packages. Although functionally similar as 3-channel delay lines, the pinout and footprint are incompatible. Redesign of the PCB land pattern and signal routing is required to integrate DS1135Z-8/T&R into legacy DS1013/DS1035-based systems.
What is the maximum capacitive load DS1135Z-8/T&R can drive while maintaining specified delay and edge performance?
The DS1135Z-8/T&R is characterized to drive one 74F04-equivalent input gate (≈15 pF load) while meeting all AC specifications including 2.0–2.5 ns rise/fall times and 8 ns delay accuracy. Driving heavier loads (>20 pF) will increase propagation delay and degrade edge rates beyond datasheet limits. For higher capacitance interfaces, external buffer amplification is recommended. The DS1135Z-8/T&R output stage is rated for 12 mA sink current, limiting practical load to ≤15 pF under standard test conditions.
Does DS1135Z-8/T&R support 3.3 V logic levels or require level-shifting circuitry?
The DS1135Z-8/T&R is strictly a +5 V device: it requires VCC = 4.75–5.25 V and has VIH(min) = 2.2 V and VIL(max) = 0.8 V. While it may accept 3.3 V logic inputs (since 3.3 V > 2.2 V), output swing is rail-to-rail 0–5 V, making direct interface with 3.3 V receivers unsafe without level translation. For 3.3 V systems, use the pin-compatible DS1135L series instead. DS1135Z-8/T&R is not 3.3 V tolerant and must be used in 5 V domains only.
Is DS1135Z-8/T&R suitable for use in automotive applications?
The DS1135Z-8/T&R is qualified for industrial temperature range (-40°C to +85°C) and meets JEDEC standards for SOIC packaging, but it is not AEC-Q200 qualified or automotive-grade screened. Its datasheet specifies no automotive-specific reliability testing (e.g., HTOL, TCT, ESD HBM >2 kV). For automotive applications, Maxim does not recommend DS1135Z-8/T&R; instead, consult ADI's automotive-qualified timing portfolio. DS1135Z-8/T&R remains appropriate for industrial, test, and computing environments meeting its specified operating conditions.
DS1135Z-8/T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 8ns
- Tap Increment:
- -
- Available Total Delays:
- 8ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135Z-8/T&R FAQ
1.How can I place an order for DS1135Z-8/T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135Z-8/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135Z-8/T&R reliable?
The price and inventory of DS1135Z-8/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135Z-8/T&R is usually 5 days.
3.What payment methods are accepted for DS1135Z-8/T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135Z-8/T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135Z-8/T&R?
DS1135Z-8/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135Z-8/T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135Z-8/T&R?
For technical support, including DS1135Z-8/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135Z-8/T&R requirements.
6.How does Aetrix verify that DS1135Z-8/T&R is sourced from the original manufacturer or authorized distributors?
All DS1135Z-8/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135Z-8/T&R meets industry standards.
7.What is the process for return or replacement of DS1135Z-8/T&R?
All DS1135Z-8/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1135Z-8/T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135Z-8/T&R part is unused and in its original packaging.
Return procedure for DS1135Z-8/T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135Z-8/T&R Tags

-
LTC6994CS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994CDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRPBF
Analog Devices Inc.

-
LTC6994IDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-1#TRMPBF
Analog Devices Inc.

-
DS1124U-25+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
