Analog Devices Inc./Maxim Integrated DS1135Z-8+T&R
- Part No.:
- DS1135Z-8+T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1135Z-8+T&R.pdf
- Description:
- IC DELAY LINE 8NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,646
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Product details
Overview
DS1135Z-8+T&R from Maxim Integrated is a high-speed, all-silicon 3-channel digital delay line operating at +5V with identical 8ns propagation delay per output (tPLH/tPHL), ±1.0ns initial tolerance, and ±1.5ns tolerance over -40°C to +85°C. It delivers precise leading/trailing edge timing for clock skew management in FPGA interface circuits and high-speed logic synchronization.
For engineers reviewing the DS1135Z-8+T&R datasheet, DS1135Z-8+T&R pinout, DS1135Z-8+T&R application, or DS1135Z-8+T&R equivalent, this page provides verified timing accuracy, SOIC-8 package mapping, industrial temperature support, and direct replacement guidance for legacy DS1013/DS1035 designs.
Technical Context
The DS1135Z-8+T&R implements three independent buffered delay paths in a single monolithic silicon circuit, each with matched tPLH and tPHL characteristics. Its architecture preserves input signal symmetry via edge-aligned delay generation, eliminating duty cycle distortion across all outputs.
It operates within 4.75V–5.25V supply range and supports full industrial temperature range (-40°C to +85°C) with guaranteed delay stability. Each output drives up to 10 LS-TTL loads while maintaining sub-nanosecond edge precision under varying voltage and thermal conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 8 ns (tPLH/tPHL), identical across OUT1–OUT3 for deterministic multi-path timing alignment |
| Initial delay tolerance | ±1.0 ns at +25°C, VCC = 5.0V - enables tight setup/hold margin control without calibration |
| Temp/voltage tolerance | ±1.5 ns over -40°C to +85°C and 4.75V–5.25V - ensures stable delay in unregulated industrial environments |
| Supply voltage | +5V ±5% - compatible with standard TTL/CMOS logic rails; not 3V-compatible (see DS1135L) |
| Output drive strength | 12 mA sink / -1.0 mA source - sufficient for direct interfacing to 74F04 inputs or 10 LS-TTL loads |
| Rise/fall time | 2.0–2.5 ns - maintains signal integrity for >200 MHz clock domains with minimal jitter contribution |
Pinout & Package
DS1135Z-8+T&R is housed in an 8-pin SOIC (150-mil) package, RoHS-compliant, vapor-phase/reflow/wave solderable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN3 | Dedicated input channels | Independent logic-level inputs accepting TTL/CMOS-compatible signals; no internal cross-coupling |
| OUT1, OUT2, OUT3 | Buffered delay outputs | Each provides identical 8ns delay with matched edge timing; capable of driving 10 LS loads |
| VCC | Positive supply rail | +5V power input; requires local 0.1 µF decoupling per device for stable delay performance |
| GND | Signal and power ground | Common reference for all inputs, outputs, and internal circuitry; must be low-impedance |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates quartz or analog RC dependencies-enables full CMOS process integration, zero aging, and immunity to mechanical shock |
| Precision edge matching | Identical tPLH and tPHL ensure preserved input duty cycle at all outputs-critical for clock forwarding and DDR strobe alignment |
| Three independent buffered delays | Enables simultaneous delay of multiple control/data lines without external fanout or buffering-reduces BOM count and layout area |
| Industrial temperature operation | Guaranteed 8ns delay performance from -40°C to +85°C-supports deployment in base stations, motor drives, and factory automation |
Applications
| FPGA Clock Skew Compensation | High-Speed Logic Synchronization |
|---|---|
Use Scenario: Aligning clock arrival times across multiple FPGA banks with differing trace lengths. IC Role / Device Role / Timing Role: Precision delay element providing matched 8ns offset on dedicated clock distribution paths. Use Value: Eliminates need for PCB-length tuning or programmable delay ICs-reduces design iteration cycles and improves timing closure predictability. | Use Scenario: Synchronizing enable signals between ASIC and memory controller in burst-mode interfaces. IC Role / Device Role / Timing Role: Three-channel delay buffer ensuring deterministic setup/hold margins for parallel data capture windows. Use Value: Maintains signal integrity across all edges with <2.5ns rise/fall time-prevents metastability in high-throughput data pipelines. |
| Industrial PLC Input Debouncing | Test Equipment Signal Conditioning |
Use Scenario: Adding consistent 8ns delay to digital I/O lines in programmable logic controllers to suppress contact bounce artifacts. IC Role / Device Role / Timing Role: Fixed-delay filter inserted inline with sensor input paths before sampling latches. Use Value: Provides repeatable, temperature-stable delay without software overhead or microcontroller resource usage-improves real-time determinism. | Use Scenario: Calibrating time-of-flight offsets in automated test equipment channel timing modules. IC Role / Device Role / Timing Role: Reference delay standard used to verify instrument channel skew and jitter performance. Use Value: Delivers ±1.5ns max variation over full industrial temperature range-enables traceable, NIST-aligned calibration workflows. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1135Z-6+T&R | 6ns nominal delay (vs. 8ns); same SOIC-8 package, temp range, and drive capability | Suitable where shorter delay is required for tighter timing budgets-e.g., short-trace FPGA I/O compensation | Select when exact 6ns offset is needed; not interchangeable without timing revalidation |
| DS1135Z-10+T&R | 10ns nominal delay (vs. 8ns); identical AC/DC specs, package, and reliability profile | Preferred for longer interconnect delays or added margin in noisy industrial environments | Choose for increased setup/hold safety margin; requires PCB-level timing analysis update |
Compared with DS1135Z-6+T&R and DS1135Z-10+T&R, the DS1135Z-8+T&R offers the optimal balance of delay headroom and signal fidelity for mid-range trace-length mismatches in industrial control and communications hardware-avoiding over-design while preserving edge precision.
Availability
DS1135Z-8+T&R is available at Aetrix Electronics and suitable for FPGA clock alignment, high-speed logic synchronization, and industrial PLC timing applications requiring stable component supply across extended production lifecycles.
Supply support for DS1135Z-8+T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated is a U.S.-based semiconductor company specializing in analog and mixed-signal ICs for power, sensing, and timing applications.
The DS1135 series was designed as a high-reliability, all-silicon replacement for aging hybrid delay solutions-targeting industrial, communications, and test equipment where long-term timing stability and solderability are critical.
FAQ
What is the guaranteed delay accuracy of DS1135Z-8+T&R over its full operating temperature range?
The DS1135Z-8+T&R guarantees ±1.5ns delay tolerance over -40°C to +85°C and 4.75V–5.25V supply. This applies to both tPLH and tPHL measurements at the 1.5V threshold, ensuring matched rising/falling edge behavior across all three outputs under industrial environmental stress.
Can DS1135Z-8+T&R operate from a 3.3V supply?
No, DS1135Z-8+T&R is specified only for +5V operation (4.75V–5.25V). For 3V-compatible operation, Maxim recommends the DS1135L family. Using DS1135Z-8+T&R below 4.75V may result in undefined delay behavior, reduced noise margin, or failure to meet AC specifications.
Is DS1135Z-8+T&R pin-compatible with DS1013 or DS1035?
Yes, DS1135Z-8+T&R uses the same 8-pin SOIC (150-mil) footprint and pin assignment as DS1013 and DS1035. It is explicitly recommended by Maxim as a drop-in replacement, retaining identical IN1–IN3, OUT1–OUT3, VCC, and GND connections without PCB modification.
What load can each output of DS1135Z-8+T&R drive reliably?
Each DS1135Z-8+T&R output drives up to 10 LS-TTL loads (equivalent to one 74F04 input gate per output) while maintaining specified rise/fall times and delay accuracy. Exceeding this load increases propagation delay variation and may degrade edge fidelity beyond datasheet limits.
Does DS1135Z-8+T&R require external decoupling capacitors?
Yes, DS1135Z-8+T&R requires a minimum 0.1 µF ceramic capacitor placed as close as possible to the VCC and GND pins. This decoupling is essential to maintain delay stability and minimize supply-induced jitter-especially under fast-switching load conditions or in noisy industrial power environments.
DS1135Z-8+T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 8ns
- Tap Increment:
- -
- Available Total Delays:
- 8ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1135Z-8+T&R FAQ
1.How can I place an order for DS1135Z-8+T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1135Z-8+T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1135Z-8+T&R reliable?
The price and inventory of DS1135Z-8+T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1135Z-8+T&R is usually 5 days.
3.What payment methods are accepted for DS1135Z-8+T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1135Z-8+T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1135Z-8+T&R?
DS1135Z-8+T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1135Z-8+T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1135Z-8+T&R?
For technical support, including DS1135Z-8+T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1135Z-8+T&R requirements.
6.How does Aetrix verify that DS1135Z-8+T&R is sourced from the original manufacturer or authorized distributors?
All DS1135Z-8+T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1135Z-8+T&R meets industry standards.
7.What is the process for return or replacement of DS1135Z-8+T&R?
All DS1135Z-8+T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1135Z-8+T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1135Z-8+T&R part is unused and in its original packaging.
Return procedure for DS1135Z-8+T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1135Z-8+T&R Tags

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