Analog Devices Inc./Maxim Integrated DS1231S-50+

Overview

DS1231S-50+ from Maxim Integrated is a power monitor IC that detects impending power failure by monitoring both high-voltage input (IN) and +5V supply (VCC), provides dual reset outputs (RST active-high, RST active-low open-drain), generates non-maskable interrupt (NMI), and supports 5% or 10% VCC threshold detection via TOL pin-used in industrial control systems for orderly processor shutdown before hold-up time exhaustion.

For engineers reviewing the DS1231S-50+ datasheet, DS1231S-50+ pinout, DS1231S-50+ application, or DS1231S-50+ equivalent, key selection criteria include VCC trip accuracy (±5% at 4.50–4.74V with TOL=GND), IN pin hysteresis (+60 mV), dual-mode input interface (high-Z or 30 µA current source), NMI-to-RST timing margin (≥200 µs), and SOIC-16 package compatibility with legacy DIP-8 footprint layouts.

Technical Context

The DS1231S-50+ integrates two independent comparators: one monitors VCC against temperature-compensated reference to assert RST/RST at selectable 4.5V (10%) or 4.25V (5%) thresholds; the other monitors IN pin voltage with mode-selectable input characteristics-high-impedance (Mode=VCC, VTP−=2.3V) or 30 µA current source (Mode=GND, VTP+=2.5V).

It delivers precise power-fail warning via NMI with 1.1 µs propagation delay, ensures robust noise immunity through 60 mV hysteresis on IN, guarantees minimum 150 ms power-up reset assertion, and maintains RST/RST output states until VCC drops below 2.0V-enabling fail-safe microprocessor halt prior to nonvolatile memory corruption.

Key Specifications

Pinout & Package

DS1231S-50+ is housed in a 16-pin SOIC (300 mil) surface-mount package with 0.050" lead pitch and standard JEDEC MS-012AC outline. Pin 1 is top-left corner, pin 16 bottom-right.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar power monitor applications.

Compared with MAX690CSA+ and TPS3823-50DBVR, DS1231S-50+ uniquely combines dual reset polarity, NMI generation, and mode-selectable high-voltage input-making it the only option among the three capable of implementing fail-safe, multi-stage power-loss response in industrial control and medical equipment.

Availability

DS1231S-50+ is available at Aetrix Electronics and suitable for industrial PLCs, medical UPS handoff circuits, telecom line cards, and embedded data loggers requiring stable component supply with long-term lifecycle assurance.

Supply support for DS1231S-50+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, automotive, and communications markets, with emphasis on reliability and integration.

The DS1231S-50+ belongs to Maxim's power supervision product line, engineered specifically for systems demanding deterministic power-fail response, nonvolatile memory protection, and flexible high-voltage interface options in commercial-temperature environments.

FAQ

What is the function of the MODE pin on the DS1231S-50+?

The MODE pin on the DS1231S-50+ selects the electrical behavior of the IN pin: when tied to VCC, IN becomes a high-impedance input (VTP−=2.3V) for resistor-divider sensing; when grounded, IN acts as a 30 µA current source (VTP+=2.5V) for direct opto-isolator interfacing. This dual-mode capability allows DS1231S-50+ to adapt to either isolated or non-isolated power monitoring architectures without external circuit changes.

How does the TOL pin affect the reset threshold of the DS1231S-50+?

The TOL pin on the DS1231S-50+ configures the VCC trip point: grounding TOL selects a 5% threshold (4.50–4.74V), while connecting it to VCC selects a 10% threshold (4.25–4.49V). This adjustment directly determines when DS1231S-50+ asserts RST/RST during power-down-enabling system designers to match the reset timing to their power supply's hold-up capability and regulatory compliance requirements.

Why does the DS1231S-50+ have two RST outputs with different polarities?

The DS1231S-50+ provides RST (active-high push-pull) and RST (active-low open-drain) to accommodate diverse microprocessor reset architectures: RST interfaces directly with CPUs requiring active-high reset (e.g., 8051), while RST connects to systems needing active-low assertion with external pull-up (e.g., ARM Cortex-M). This dual-output design eliminates level-shifting components and ensures DS1231S-50+ interoperability across legacy and modern processor platforms.

Does the DS1231S-50+ require external capacitors for reset timing?

No, the DS1231S-50+ requires no external capacitors for reset timing-the internal temperature-compensated reference and digital delay circuitry generate precise 150 ms minimum power-up reset assertion and accurate VCC trip detection. This capacitor-free operation reduces bill-of-materials cost, improves reliability, and simplifies PCB layout compared to RC-based reset ICs, making DS1231S-50+ ideal for space-constrained and high-reliability applications.

What is the purpose of the 60 mV hysteresis on the IN pin of the DS1231S-50+?

The 60 mV hysteresis on the IN pin of the DS1231S-50+ prevents chatter-induced false NMI assertions during noisy AC line conditions or slow-rising/falling input voltages. It ensures clean, single-event NMI generation even under marginal power conditions-critical for DS1231S-50+'s role in initiating reliable processor shutdown sequences without spurious interrupts that could corrupt nonvolatile memory operations.