My Inquiry
My Account
Analog Devices Inc./Maxim Integrated DS1236A-5+
- Part No.:
- DS1236A-5+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
DS1236A-5+.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16DIP
- Quantity:
- Payment:
- Shipping:
Inventory:180
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1236A-5+ from Maxim Integrated is a microprocessor supervisory IC that provides power-fail detection, reset control, nonvolatile SRAM backup, watchdog timer, and early-warning NMI generation for embedded systems. It features 4.75 V (typ. 4.62 V) 5% VCC trip point, <100 nA battery current at 25°C, and dual active-high/active-low RST outputs. Used in battery-backed data loggers and industrial controllers requiring orderly shutdown.
For engineers reviewing the DS1236A-5+ datasheet, DS1236A-5+ pinout, DS1236A-5+ application, or DS1236A-5+ equivalent, key selection criteria include precise 5% VCC monitoring threshold, VCCO-controlled SRAM write protection timing, NMOS/CMOS mode selection via RC pin, and integrated pushbutton debouncing with 25 ms minimum reset pulse width.
Technical Context
The DS1236A-5+ implements a bandgap-referenced comparator for accurate 5% VCC monitoring (VCCTP = 4.75 V), generating active-high PF and dual RST outputs on out-of-tolerance conditions. Its internal watchdog timer provides 100–600 ms timeout with ST input strobing, while the IN pin enables user-configurable early-warning voltage sensing at 2.54 V threshold.
Reset behavior is mode-dependent: NMOS mode (RC = GND) asserts RST/RST continuously during VCC decay below VCCTP; CMOS mode (RC = VCCO) suppresses reset but pulses NMI for sleep-mode entry and relies on VCCO to maintain SRAM and processor state. CEO output enforces unconditional SRAM write protection within 7–44 μs of VCC failure.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Trip Point | 4.75 V (min), 4.62 V typical - triggers reset and PF outputs when 5 V supply falls below 5% tolerance. |
| Battery Current (IBAT) | <100 nA at 25°C - enables multi-year operation on coin-cell batteries in standby. |
| RST Active Duration | 25 ms minimum - ensures reliable microprocessor initialization after power recovery. |
| Watchdog Timeout | 100–600 ms - detects software hang by requiring ST strobe; resets if unstimulated. |
| NMI Pulse Width | 200–500 μs - delivers deterministic early-warning interrupt before VCC collapse. |
| VCCO Output Capability | 1 mA at VBAT−0.7 V - sustains SRAM data retention during main supply loss. |
| IN Pin Threshold (VTP) | 2.50–2.60 V - sets early-warning voltage sense point for customizable power-fail detection. |
Pinout & Package
DS1236A-5+ is available in 16-pin SOIC (300-mil) and 16-pin DIP packages. Both variants share identical pin functions and electrical characteristics.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBAT | +3 V battery input | Provides backup power path for nonvolatile operation of control logic and VCCO switching. |
| VCCO | Switched SRAM supply output | Delivers higher-of-VCC/VBAT to SRAM; enables seamless switchover during power loss. |
| VCC | +5 V primary supply input | Main system power source; monitored for 5% out-of-tolerance condition per DS1236A-5+ variant. |
| GND | Ground reference | Common return for all analog and digital circuitry; required for accurate comparator operation. |
| PF / PF | Power-fail indicators (active high/low) | Drive external MOSFETs or load switches to manage high-current backup transitions. |
| WC/SC | Wake-up/Sleep control | Disables comparators and enters ultra-low-power sleep mode when asserted. |
| RC | Reset control selection | Determines NMOS (GND) vs. CMOS (VCCO) mode - defines RST/NMI timing and battery isolation behavior. |
| IN | Early-warning voltage sense input | High-impedance node for resistor-divider configuration; triggers NMI at 2.54 V threshold. |
| NMI | Non-maskable interrupt output | Pulses low for 200–500 μs to signal impending power failure before VCC collapse. |
| ST | Strobe input | Resets watchdog timer on high-to-low transition; prevents spurious reset during normal software execution. |
| CEO | Chip enable output | Drives SRAM CE to write-protect memory within 7–44 μs of VCC failure. |
| CEI | Chip enable input | Allows external control of CEO; delays write protection until current memory cycle completes. |
| PBRST | Pushbutton reset input | Debounced active-low input; generates 25 ms minimum RST pulse on button release. |
| RST / RST | Reset outputs (active low/high) | Simultaneously assert complementary signals for NMOS/CMOS processor compatibility. |
Key Features
| Feature | Design Value |
|---|---|
| 5% precision VCC monitoring | Guarantees reset activation at 4.75 V (DS1236A-5+) - tighter than standard 10% variants for critical brownout immunity. |
| Configurable NMOS/CMOS mode | RC pin selection determines whether RST remains active during power loss (NMOS) or NMI initiates sleep (CMOS), enabling one IC across two architecture classes. |
| Integrated SRAM backup control | VCCO switching + CEO-driven write protection eliminates need for external diodes, regulators, and logic to secure volatile memory during power interruption. |
| Programmable early-warning NMI | IN pin accepts user-defined voltage divider to detect supply degradation at any point above 2.54 V - extends shutdown window beyond fixed VCC trip. |
| Hardware-debounced pushbutton reset | PBRST pin includes internal 10 kΩ pull-up and timing circuitry - removes need for external RC filters or firmware debounce routines. |
| Watchdog with configurable disable | ST input resets 100–600 ms timer; watchdog can be disabled by grounding IN (CMOS mode) or leaving ST open - avoids unintended resets in simple applications. |
Applications
| Industrial Data Logger | Medical Patient Monitor |
|---|---|
Use Scenario: Continuous sensor sampling with local flash storage during AC mains outage. IC Role / Device Role / Timing Role: DS1236A-5+ monitors 5 V rail, triggers NMI at 4.8 V to initiate data flush, then asserts RST at 4.75 V to halt CPU while VCCO sustains SRAM and flash controller. Use Value: Prevents data corruption by guaranteeing ≥200 μs warning before reset, with write protection enforced within 44 μs of VCC drop. |
Use Scenario: Battery-powered bedside monitor storing vital signs during hospital power failure. IC Role / Device Role / Timing Role: DS1236A-5+ uses VBAT to maintain real-time clock and SRAM; RC pin set to VCCO enables CMOS sleep mode, reducing system current to <10 μA. Use Value: Extends battery life >3× versus always-on supervision; NMI pulse wakes CPU only when action is required, not on every minor fluctuation. |
| Point-of-Sale Terminal | Smart Energy Meter |
Use Scenario: Transaction logging during brief grid sags common in retail environments. IC Role / Device Role / Timing Role: DS1236A-5+ detects 5% VCC dip (4.75 V) and holds RST active for 25 ms minimum, ensuring EEPROM write completion before power loss. Use Value: Eliminates need for supercapacitor hold-up circuits - reduces BOM cost and board space while meeting EN 61000-4-11 immunity requirements. |
Use Scenario: Tamper-resistant meter retaining billing data and time-of-use logs during utility outages. IC Role / Device Role / Timing Role: DS1236A-5+ drives external PF-controlled MOSFET to switch from line power to lithium-thionyl chloride battery, with CEO write-protecting metrology RAM. Use Value: Achieves >10-year battery life via <100 nA quiescent current; PF/PF outputs handle >500 mA load switching without external drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX690TSA+ | Fixed 4.65 V reset threshold; no NMI output; no VCCO switching; 16-pin SOIC only. | Lacks early-warning interrupt and SRAM backup control - suitable only for basic reset-only use cases. | Select when only power-on/power-fail reset is needed and NMI/VCCO functionality is unused. |
| TPS3823MPW | Adjustable reset threshold (via external resistor); 200 ms reset timeout; no watchdog or NMI; 8-pin SOIC. | No memory backup support or pushbutton reset - targets low-pin-count applications with programmable trip points. | Choose for cost-sensitive designs where adjustable threshold outweighs need for integrated SRAM control. |
Compared with MAX690TSA+ and TPS3823MPW, DS1236A-5+ uniquely integrates 5% precision monitoring, NMI-based predictive shutdown, VCCO-controlled SRAM backup, and hardware-debounced PBRST - making it the only solution requiring no external components for full nonvolatile system supervision.
Availability
DS1236A-5+ is available at Aetrix Electronics and suitable for industrial data loggers, medical patient monitors, point-of-sale terminals, and smart energy meters requiring stable component supply and long-term lifecycle support.
Supply support for DS1236A-5+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, automotive, and communications applications, with emphasis on reliability and integration.
The DS1236A product line delivers integrated power supervision, memory backup, and reset control for microprocessor systems - specifically engineered to replace discrete supervisor + battery-switch + watchdog solutions in space-constrained, battery-backed equipment.
FAQ
What is the exact VCC trip point specification for DS1236A-5+?
The DS1236A-5+ has a guaranteed VCC trip point of 4.75 V minimum, 4.62 V typical, and 4.50 V maximum - corresponding to a 5% tolerance on a nominal 5 V supply. This is distinct from the standard DS1236A (10% option, 4.50 V trip). The value is factory-trimmed and specified over 0°C to 70°C operating temperature.
How does DS1236A-5+ handle SRAM write protection during power loss?
DS1236A-5+ enforces unconditional SRAM write protection by driving CEO high within 7–44 μs of VCC falling below VCCTP. If CEI is low during power failure, CEO remains latched until CEI returns high or tCE (5 s) expires - preventing data corruption mid-cycle. VCCO simultaneously switches to VBAT to sustain SRAM voltage.
Can DS1236A-5+ operate without a battery connected to VBAT?
Yes, DS1236A-5+ can operate with VBAT grounded, functioning as a reset supervisor only. In this configuration, RC must be tied to GND (NMOS mode), and VCCO is disabled. All power-fail detection, reset generation, watchdog, and pushbutton functions remain fully operational - but SRAM backup and NMI-based sleep mode are unavailable.
What is the purpose of the WC/SC pin on DS1236A-5+?
The WC/SC (Wake-up/Sleep Control) pin disables internal comparators and places DS1236A-5+ into ultra-low-power sleep mode when asserted. This reduces supply current to 20 μA and halts NMI, RST, and watchdog activity - extending battery life in handheld devices. Wake-up occurs via PBRST, VCC rise above VBAT, or external assertion of WC/SC.
How is the early-warning NMI function configured on DS1236A-5+?
The NMI function is configured using the IN pin, which senses voltage via an external resistor divider. With VTP = 2.54 V, selecting R1 and R2 per the equation VSENSE = R2/(R1+R2) × 2.54 sets the early-warning threshold. For example, a 4.80 V sense point requires R1 = 8.9 kΩ with R2 = 10 kΩ - enabling NMI assertion before VCC reaches 4.75 V.
DS1236A-5+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- MicroManager
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.62V
- Output:
- Open Drain, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- 25ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
DS1236A-5+ FAQ
1.How can I place an order for DS1236A-5+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1236A-5+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1236A-5+ reliable?
The price and inventory of DS1236A-5+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1236A-5+ is usually 5 days.
3.What payment methods are accepted for DS1236A-5+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1236A-5+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1236A-5+?
DS1236A-5+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1236A-5+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1236A-5+?
For technical support, including DS1236A-5+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1236A-5+ requirements.
6.How does Aetrix verify that DS1236A-5+ is sourced from the original manufacturer or authorized distributors?
All DS1236A-5+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1236A-5+ meets industry standards.
7.What is the process for return or replacement of DS1236A-5+?
All DS1236A-5+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1236A-5+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1236A-5+ part is unused and in its original packaging.
Return procedure for DS1236A-5+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1236A-5+ Tags
-
MIC826SYMT-TR
Microchip Technology
-
APX803S-31SA-7
Diodes Incorporated
-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments
-
V6340RSP3B+
EM Microelectronic
-
EM6325CXSP5B-2.9+
EM Microelectronic
-
MCP120T-300I/TT
Microchip Technology
-
MCP130T-315I/TT
Microchip Technology
-
MCP120T-475I/TT
Microchip Technology
-
MCP111T-300E/TT
Microchip Technology
-
MCP120T-315I/TT
Microchip Technology
-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
