Analog Devices Inc./Maxim Integrated DS1236N-5+
- Part No.:
- DS1236N-5+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
DS1236N-5+.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1236N-5+ from Maxim Integrated is a microprocessor supervisory IC providing power-fail detection, reset control, nonvolatile SRAM backup, watchdog timer, and early-warning NMI generation for 5V systems. It features 4.75V ±5% VCC trip point, <100nA battery current at 25°C, and dual active-high/active-low RST outputs. Used in battery-backed embedded controllers requiring orderly shutdown and data retention.
For engineers reviewing the DS1236N-5+ datasheet, DS1236N-5+ pinout, DS1236N-5+ application, or DS1236N-5+ equivalent, key selection criteria include precise 5% power-supply monitoring threshold, VCCO switched SRAM supply capability, integrated pushbutton reset debouncing, NMOS/CMOS mode selection via RC pin, and industrial temperature support (–40°C to +85°C).
Technical Context
The DS1236N-5+ integrates a bandgap voltage reference and precision comparator for accurate 5% VCC monitoring (VCCTP = 4.75V typ), with 100μs typical response time from VCC drop to RST assertion. Its dual-mode reset control (RC pin) configures timing and polarity for NMOS (RC = GND) or CMOS (RC = VCCO) processors, enabling either continuous reset during power loss or pulsed NMI for sleep-mode entry.
It embeds a 400ms typical watchdog timer (100–600ms range) triggered by ST strobe absence, plus an early-warning circuit using the IN pin (VTP = 2.54V) to generate a 200–500μs NMI pulse upon voltage decay. The chip also provides VCCO switching between VCC and VBAT (2.7–4.0V), CEO-controlled SRAM write protection, and PF/PF outputs for external power-switching control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Trip Point | 4.75V (±0.25V), enables precise 5% undervoltage detection for critical 5V systems |
| Battery Current (IBAT) | <100 nA at 25°C, ensures multi-year backup operation on coin-cell batteries |
| RST Active Duration | 25–150 ms minimum, guarantees full microprocessor initialization before release |
| Watchdog Timeout | 400 ms typical (100–600 ms max), provides robust software hang detection without false triggers |
| NMI Pulse Width | 200–500 μs, delivers unambiguous early warning of impending power failure |
| VCCO Output Capability | 100 mA at VCC−0.3V, supports direct powering of standard 32k×8 SRAMs |
| IN Pin Trip Voltage | 2.54V (2.5–2.6V), allows flexible external resistor-divider setup for custom voltage sensing |
Pinout & Package
DS1236N-5+ is available in 16-pin SOIC (300-mil) and 16-pin DIP packages. Both share identical pin mapping and electrical behavior.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBAT | +3V Battery Input | Provides nonvolatile operation of control logic and VCCO switching when VCC fails |
| VCCO | Switched SRAM Supply Output | Delivers higher-of-VCC-or-VBAT to SRAM, enabling seamless battery backup |
| VCC | +5V Primary Power Input | Main system supply monitored for 4.75V trip; powers internal logic and I/O |
| GND | Ground Reference | Common return path for all analog and digital circuits; required for comparator accuracy |
| PF / PF | Power-Fail Indicators (Active High/Low) | Drive external MOSFETs or PMICs to switch load between VCC and battery |
| WC/SC | Wake-Up/Sleep Control | Disables comparators and enters ultra-low-power sleep mode when asserted |
| RC | Reset Control | Selects NMOS (GND) or CMOS (VCCO) mode, determining RST/NMI timing and polarity |
| IN | Early Warning Input | High-impedance sense node for user-defined voltage threshold (VTP = 2.54V) |
| NMI | Non-Maskable Interrupt | Pulsed output signaling imminent power loss; used to initiate controlled shutdown |
| ST | Strobe Input | Resets watchdog timer; must be toggled every ≤100 ms to prevent timeout reset |
| CEO | Chip Enable Output | Drives SRAM CE low during power fail to unconditionally write-protect memory |
| CEI | Chip Enable Input | Allows synchronization of CEO assertion with ongoing memory access cycles |
| PBRST | Pushbutton Reset Input | Debounced, active-low input triggering 25 ms minimum RST pulse on button release |
| RST / RST | Reset Outputs (Active Low/High) | Dual-polarity reset signals compatible with NMOS (low-active) and CMOS (high-active) processors |
Key Features
| Feature | Design Value |
|---|---|
| 5% Precision Power Monitoring | VCCTP = 4.75V (DS1236N-5+) ensures tighter tolerance than standard 10% variants for mission-critical 5V rails |
| Configurable Processor Mode | RC pin selects NMOS (continuous reset) or CMOS (NMI-triggered sleep) behavior-no hardware change needed |
| Integrated SRAM Backup Control | VCCO switching + CEO-driven write protection eliminates need for external diodes, regulators, or logic |
| Programmable Early Warning | IN pin with 2.54V threshold enables custom voltage sensing points (e.g., 12V rail via resistor divider) |
| Ultra-Low Battery Drain | <100 nA IBAT extends coin-cell life beyond 10 years in storage or standby |
| External Power Switch Support | PF/PF outputs rated for direct drive of discrete MOSFETs or load switches in high-current backup paths |
Applications
| Industrial Data Logger | Medical Patient Monitor |
|---|---|
Use Scenario: Continuous sensor sampling with periodic flash writes; power may fail unpredictably during data capture. IC Role / Device Role: DS1236N-5+ monitors VCC, asserts NMI to trigger immediate RAM-to-flash save, then holds RST until safe shutdown completes. Use Value: Prevents corruption of last-recorded vital signs by guaranteeing ≥200μs NMI warning before 4.75V trip and 25ms reset hold. |
Use Scenario: Portable ECG unit operating on rechargeable Li-ion with backup coin cell; requires zero-data-loss during AC dropout. IC Role / Device Role: DS1236N-5+ switches SRAM supply to VBAT, pulses NMI at 4.8V (via R1/R2 divider), and forces CEO high to lock memory before VCC falls below 4.75V. Use Value: Enables deterministic 2.54V-sensed early warning and <100nA battery drain-critical for FDA-compliant 72-hour backup runtime. |
| Point-of-Sale Terminal | Smart Energy Meter |
Use Scenario: Transaction processing interrupted by brownout; EEPROM writes must complete or abort cleanly. IC Role / Device Role: DS1236N-5+ detects 4.75V VCC collapse, disables CPU via RST, asserts CEO to freeze SRAM, and activates PF to switch auxiliary power. Use Value: Eliminates need for external supervisor + power switch IC, reducing BOM count while meeting PCI PTS 6.1 power-fail recovery requirements. |
Use Scenario: Utility meter logging kWh data to FRAM; mains power may cycle frequently in rural grids. IC Role / Device Role: DS1236N-5+ uses WC/SC to enter sleep mode between readings, wakes on PBRST or VCC rise, and delivers 25ms reset pulse on every power-up. Use Value: Achieves <1μA system sleep current (with CMOS processor) and guarantees 100% reliable reset timing across –40°C to +85°C operating range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX690TSA+ | Fixed 4.65V trip (±1.5%), no NMI output, no VCCO switching, 10μA quiescent current | Lacks early warning and SRAM backup functions; suitable only for basic reset-only use cases | Choose MAX690TSA+ only if system uses separate SRAM backup circuitry and does not require NMI-based shutdown sequencing |
| TPS3823MPW | 4.63V trip (±0.5%), 200ms fixed reset timeout, no watchdog, no battery input, 15μA supply current | Designed for single-supply systems without battery backup; no VBAT interface or CEO control | Use TPS3823MPW where battery-free operation is mandatory and precise 4.75V trip is secondary to ultra-low cost |
Compared with DS1236N-5+, MAX690TSA+ omits critical NMI and VCCO functions needed for graceful shutdown, while TPS3823MPW lacks battery interface and configurable reset modes-making DS1236N-5+ the sole option supporting full nonvolatile SRAM + processor backup with 5% trip accuracy.
Availability
DS1236N-5+ is available at Aetrix Electronics and suitable for industrial data loggers, medical patient monitors, point-of-sale terminals, and smart energy meters requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for DS1236N-5+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for demanding industrial, medical, and communications applications.
The DS1236N-5+ belongs to Maxim's MicroManager family-engineered specifically for microprocessor-based systems needing coordinated power monitoring, reset, memory backup, and orderly shutdown in battery-critical environments.
FAQ
What is the exact VCC trip voltage specification for DS1236N-5+?
The DS1236N-5+ has a guaranteed VCC trip point of 4.75V ±0.25V (min 4.50V, max 4.75V), with 4.62V typical. This 5% tolerance is factory-trimmed and distinct from the standard DS1236 (10% trip at 4.5V). The DS1236N-5+ datasheet specifies VCCTP under "DC Electrical Characteristics" Table, confirming it meets industrial-grade accuracy for critical 5V rail supervision.
Does DS1236N-5+ support both active-high and active-low reset outputs simultaneously?
Yes, DS1236N-5+ provides two independent reset outputs: RST (active low) and RST (active high), both asserted concurrently during power-fail or watchdog timeout. This dual-polarity capability allows direct interfacing with NMOS processors (requiring low-active reset) and CMOS processors (requiring high-active reset) without external inverters-verified in the "Pin Description" and "Timing Diagrams" sections of the DS1236N-5+ datasheet.
How does DS1236N-5+ handle SRAM write protection during power failure?
DS1236N-5+ unconditionally asserts CEO high within 7–44μs of VCC falling below VCCTP, forcing external SRAM into write-protected state. If CEI is low during fail, CEO remains latched until CEI goes high or tCE (5 seconds) expires-ensuring no partial writes corrupt memory. This behavior is explicitly defined in the "Memory Backup" section and confirmed by timing parameter tCF in the DS1236N-5+ datasheet.
Can DS1236N-5+ operate with a 3.3V main supply?
No, DS1236N-5+ is specified only for 4.5–5.5V VCC operation per its "Recommended DC Operating Conditions." It lacks 3.3V compatibility-attempting 3.3V operation violates absolute maximum ratings and disables internal comparators. For 3.3V systems, designers must select alternatives like MAX6369 or TPS3808, as DS1236N-5+ functionality is strictly bound to 5V rail supervision.
What is the purpose of the WC/SC pin on DS1236N-5+ and how is it used?
The WC/SC (Wake-up/Sleep Control) pin on DS1236N-5+ disables all internal comparators and enters ultra-low-power sleep mode when driven high, reducing supply current to 20μA. It is used to conserve battery during idle periods in handheld devices. Wake-up occurs on PBRST press, VCC rise above VBAT, or external assertion-details are fully documented in the "Wake Control/Sleep Control" section of the DS1236N-5+ datasheet.
DS1236N-5+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- MicroManager
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.62V
- Output:
- Open Drain, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- 25ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
DS1236N-5+ FAQ
1.How can I place an order for DS1236N-5+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1236N-5+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1236N-5+ reliable?
The price and inventory of DS1236N-5+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1236N-5+ is usually 5 days.
3.What payment methods are accepted for DS1236N-5+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1236N-5+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1236N-5+?
DS1236N-5+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1236N-5+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1236N-5+?
For technical support, including DS1236N-5+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1236N-5+ requirements.
6.How does Aetrix verify that DS1236N-5+ is sourced from the original manufacturer or authorized distributors?
All DS1236N-5+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1236N-5+ meets industry standards.
7.What is the process for return or replacement of DS1236N-5+?
All DS1236N-5+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1236N-5+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1236N-5+ part is unused and in its original packaging.
Return procedure for DS1236N-5+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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