Analog Devices Inc./Maxim Integrated DS1236S-5

Overview

DS1236S-5 from Maxim Integrated is a microprocessor supervisory IC providing power-fail detection, reset control, nonvolatile SRAM backup, watchdog timer, and early-warning NMI generation. It features 5% VCC trip point (4.75 V typical), <100 nA battery current at 25°C, and dual active-high/active-low RST outputs. Used in battery-backed embedded systems requiring orderly shutdown and memory retention.

For engineers reviewing the DS1236S-5 datasheet, DS1236S-5 pinout, DS1236S-5 application, or DS1236S-5 equivalent, key selection criteria include its precise 5% supply monitoring threshold, VCCO switched-SRAM supply capability, integrated watchdog timeout (400 ms typ), NMOS/CMOS mode selection via RC pin, and support for industrial temperature range (-40°C to +85°C).

Technical Context

The DS1236S-5 implements a bandgap-referenced precision comparator for VCC monitoring with factory-trimmed 5% tolerance (VCCTP = 4.75 V typ), enabling earlier power-fail detection than standard 10% variants. Its dual RST outputs (active-high and active-low) and configurable RC pin allow direct interface with both NMOS and CMOS processors.

It integrates a 400 ms typical watchdog timer triggered by ST input strobing, an early-warning NMI generator tied to user-defined IN voltage threshold (VTP = 2.54 V), and bidirectional VCCO switching between VCC and VBAT to sustain SRAM during main supply loss - all while consuming <0.1 µA battery current in data-retention mode.

Key Specifications

Pinout & Package

DS1236S-5 is available in 16-pin SOIC (300-mil) package, pin-compatible with 16-pin DIP. Package dimensions comply with JEDEC MS-012AC.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with DS1236S-5, MAX690S and DS1233M omit critical functions required for nonvolatile operation-including NMI-driven shutdown, VCCO-based SRAM backup, and RC-configurable processor mode-making them unsuitable replacements in battery-backed data retention systems.

Availability

DS1236S-5 is available at Aetrix Electronics and suitable for industrial data loggers, medical patient monitors, point-of-sale terminals, and smart energy meters requiring stable component supply and long-term lifecycle support.

Supply support for DS1236S-5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in analog, mixed-signal, and power management ICs for industrial, automotive, and computing applications.

The DS1236S-5 belongs to Maxim's MicroManager family of supervisory ICs, designed specifically for reliable power monitoring, reset control, and nonvolatile memory backup in battery-critical embedded systems.

FAQ

What is the exact VCC trip point specification for DS1236S-5?

The DS1236S-5 has a factory-trimmed 5% VCC trip point with a typical value of 4.75 V (range: 4.50 V to 4.75 V). This is distinct from the standard DS1236 (10% option, 4.37 V typical) and enables earlier power-fail detection for systems with tighter supply margins. The trip point is guaranteed over temperature and voltage tolerances per the datasheet's DC electrical characteristics table.

How does DS1236S-5 support nonvolatile SRAM operation?

The DS1236S-5 supports nonvolatile SRAM through two integrated functions: (1) VCCO pin automatically sources power from the higher of VCC or VBAT, sustaining SRAM during main supply loss; and (2) CEO output is forced high during VCC failure to unconditionally write-protect SRAM, preventing data corruption. These functions operate without external components and are active across the full industrial temperature range.

Can DS1236S-5 generate both active-high and active-low reset signals simultaneously?

Yes, DS1236S-5 provides dual RST outputs: one active-low and one active-high. Both signals are asserted simultaneously when VCC falls below the 5% trip threshold (4.75 V typ) or when the watchdog times out. Their timing and polarity are independent of RC pin configuration, ensuring compatibility with both legacy NMOS and modern CMOS processors in the same design.

What is the role of the RC pin on DS1236S-5, and how does it affect system behavior?

The RC pin on DS1236S-5 selects processor interface mode: grounded for NMOS systems (continuous RST hold during power loss) or tied to VCCO for CMOS systems (NMI pulse followed by sleep-mode support). This single-pin configuration determines RST/NMI timing, CEO behavior, and watchdog interaction-enabling one DS1236S-5 design to serve both processor architectures without layout changes.

Does DS1236S-5 include a watchdog timer, and how is it configured?

Yes, DS1236S-5 includes an internal watchdog timer with a typical timeout of 400 ms (100–600 ms range). It is enabled by default and reset by a high-to-low transition on the ST pin. To disable it permanently in CMOS mode, ground the IN pin; in NMOS mode, the watchdog remains active unless VCC falls below VCCTP. No external components are required for basic operation.