Analog Devices Inc./Maxim Integrated DS1238AS-10
- Part No.:
- DS1238AS-10
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
DS1238AS-10.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:300
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1238AS-10 from Dallas Semiconductor (now Maxim Integrated) is a microprocessor supervisory IC providing power-fail detection, watchdog timer, non-maskable interrupt, battery-backed SRAM control, and dual active-low/active-high reset outputs. It monitors +5V supply with 10% trip point (4.25–4.50 V), consumes <200 nA battery current, and supports 16-pin SOIC/DIP packaging. Used in industrial embedded systems requiring orderly shutdown and data retention during brownouts.
For engineers reviewing the DS1238AS-10 datasheet, DS1238AS-10 pinout, DS1238AS-10 application, or DS1238AS-10 equivalent, key selection considerations include its 4.37 V typical VCCTP, 2.7 s internal watchdog timeout, VCCO output for SRAM backup, RVT threshold indicator, and PF-driven external power switching capability.
Technical Context
The DS1238AS-10 integrates a bandgap voltage reference and precision comparator to monitor VCC against a 4.37 V typical trip point, asserting RST/RST and RVT within 100 µs of out-of-tolerance detection. Its early-warning NMI circuit samples the IN pin at ~30 kHz with triple-sampling hysteresis to reject noise.
A programmable watchdog timer uses either internal oscillator (2.7 s long period) or external clock/capacitor timing; ST input must be strobed low before timeout to prevent reset. OSCSEL and OSCIN configure timing source, while CEO provides controlled chip-enable gating for SRAM write protection with tCE = 5 µs delay.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Power Supply Trip Point | 4.25–4.50 V (10% tolerance); ensures reset activation before microprocessor instability at VCC < 4.5 V |
| Battery Current (IBAT) | <200 nA at VBAT = 3.0 V; enables multi-year SRAM data retention on coin cell |
| Reset Pulse Width (tRST) | 40–150 ms (typ 85 ms); meets minimum reset hold time for 8051, Z80, and 68K-family processors |
| Watchdog Timeout (Int. Clock) | 1.7–2.7 s (typ 2.7 s); provides sufficient software recovery window before forced reset |
| VCCO Output Capability | 100 mA at VCC−0.3 V; powers standard 32k×8 or 64k×8 CMOS SRAM during main supply loss |
| NMI Response Delay (tIPD) | 40–175 µs; delivers early warning ≥100 µs before RST assertion for controlled save operations |
| CEO Propagation Delay | 20 ns; guarantees synchronous write-protection enable relative to CEI signal edge |
Pinout & Package
DS1238AS-10 is available in 16-pin SOIC (300-mil) and 16-pin DIP packages. Both variants share identical pin mapping and thermal characteristics, rated for commercial temperature range (0°C to +70°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBAT | +3 V battery input | Provides backup power path; disconnects via freshness seal until VCC applied |
| VCCO | Switched SRAM supply output | Auto-selects higher of VCC or VBAT−0.8 V; supplies up to 100 mA to SRAM |
| VCC | +5 V primary supply input | Monitored supply rail; trip point set to 4.37 V typical for 10% tolerance |
| GND | Ground reference | Common return for all analog/digital circuits; referenced for all voltage thresholds |
| PF | Power-fail indicator (active high) | Drives external MOSFET/switch to transition load from VCC to VBAT at VCC ≈ VBAT |
| RVT | Reset voltage threshold indicator | Open-drain output active when VCC < VCCTP; used for system-level voltage status monitoring |
| OSCIN | Oscillator timing input | Accepts external clock or 47 pF capacitor for programmable watchdog/reset timing |
| OSCSEL | Oscillator select | Hi/Open = internal 2.7 s timer; Low = external clock/capacitor mode |
| IN | Early-warning sense input | High-impedance (±1 µA) node for resistor-divider setup; VTP = 1.27 V typical |
| NMI | Non-maskable interrupt output | Active-low signal triggered when IN falls below VTP; includes 100 µs noise immunity |
| ST | Watchdog strobe input | Falling edge resets watchdog timer; open = watchdog disabled |
| CEO | Chip enable output | Drives SRAM CE; held high during power fail to unconditionally write-protect memory |
| CEI | Chip enable input | Controls CEO pass-through; write protection delayed until CEI returns high or tCE expires |
| WDS | Watchdog status output | Latched active-low flag indicating timeout occurred; cleared by ST strobe or VCC recovery |
| RST | Reset output (active low) | Guaranteed 50 ms min active pulse after VCC rises above VCCTP; drives µP /RESET |
| RST | Reset output (active high) | Complementary to active-low RST; used where logic-high reset is required |
Key Features
| Feature | Design Value |
|---|---|
| Unconditional SRAM write protection | CEO forced high within 144 µs of VCC falling below VCCTP, preventing data corruption during power loss |
| Programmable watchdog timer | Configurable via OSCSEL/OSCIN for 2.7 s internal or capacitor-based timeout; ST strobe resets counter |
| Dual-reset outputs | Simultaneous active-low and active-high RST signals eliminate need for external inverters in mixed-logic systems |
| Freshness seal function | Electrically isolates VBAT until VCC is applied, preventing premature battery discharge during assembly |
| PF-driven external power switching | PF output switches load between VCC and VBAT at VCC ≈ VBAT, enabling high-current backup without internal FET limits |
Applications
| Industrial Data Logger | Point-of-Sale Terminal |
|---|---|
|
Use Scenario: Battery-backed data logger records sensor readings during AC mains failure. IC Role / Device Role / Timing Role: DS1238AS-10 detects VCC decay, asserts NMI to trigger immediate RAM save, then asserts RST after safe storage. Use Value: 100 µs NMI latency and 20 ns CEO propagation ensure no sample is lost during brownout transition. |
Use Scenario: POS terminal retains transaction buffer and configuration during brief power interruption. IC Role / Device Role / Timing Role: DS1238AS-10 gates SRAM CE via CEO and holds VCCO stable using VBAT, preserving volatile session data. Use Value: 100 mA VCCO drive and <200 nA IBAT support 10+ year coin-cell life with full 64k×8 SRAM retention. |
| Medical Diagnostic Equipment | Telecom Line Card |
|
Use Scenario: Ultrasound machine saves calibration parameters and last image frame before shutdown. IC Role / Device Role / Timing Role: DS1238AS-10 uses IN pin to monitor intermediate 12 V rail, issuing NMI earlier than main 5 V rail collapse. Use Value: Configurable IN threshold (via R1/R2 divider) enables earliest possible warning from highest system voltage node. |
Use Scenario: Carrier-grade line card maintains register state and alarm history during hot-swap power blip. IC Role / Device Role / Timing Role: DS1238AS-10's PF output controls external ideal diode controller, ensuring seamless VCC/VBAT switchover. Use Value: PF transition at VCC ≈ VBAT eliminates voltage glitch and prevents brownout-induced packet loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691CPD+ | Pin-compatible; same 10% VCCTP (4.25–4.50 V), but lacks IN/NMI input and uses fixed 1.6 s watchdog | No early-warning interrupt; requires external circuitry for NMI-equivalent functionality | Select MAX691CPD+ only if NMI is unnecessary and footprint compatibility is critical |
| TPS3823-50DBVR | Single-supply supervisor with 5.0 V ±2% threshold (4.9–5.1 V); no VCCO output, no watchdog, no NMI | Only provides reset and power-fail flag; cannot back up SRAM or replace DS1238AS-10's integrated functions | Choose TPS3823-50DBVR only for basic reset-only use cases where SRAM backup and watchdog are handled separately |
Compared with MAX691CPD+ and TPS3823-50DBVR, the DS1238AS-10 uniquely integrates SRAM power switching (VCCO), early-warning NMI, and programmable watchdog in one 16-pin package-enabling compact, single-chip power management for legacy microprocessor systems.
Availability
DS1238AS-10 is available at Aetrix Electronics and suitable for industrial data loggers, point-of-sale terminals, medical diagnostic equipment, and telecom line cards requiring stable component supply and long-term obsolescence support.
Supply support for DS1238AS-10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Dallas Semiconductor, now part of Analog Devices (via Maxim Integrated acquisition), pioneered real-time clocks, battery-backed RAM supervisors, and secure authentication ICs for industrial and embedded markets.
The DS1238A family was designed specifically for microprocessor-based systems needing coordinated power monitoring, reset control, and nonvolatile SRAM backup-targeting applications where firmware-controlled shutdown and data integrity are mission-critical.
FAQ
What is the exact power supply trip point for DS1238AS-10?
The DS1238AS-10 has a guaranteed 10% power supply monitoring threshold, with VCCTP specified from 4.25 V to 4.50 V (typical 4.37 V) at 0°C to +70°C. This ensures reliable reset assertion before most 5 V microprocessors enter undefined operation, and differs from the 5% option (DS1238A-5) which trips at 4.75 V.
Does DS1238AS-10 support both active-low and active-high reset outputs simultaneously?
Yes, DS1238AS-10 provides two dedicated RST pins: one active-low and one active-high, both asserted concurrently during power failure or watchdog timeout. This eliminates external level-shifting components in systems requiring mixed logic families or legacy processor interfaces that demand specific reset polarity.
How does the DS1238AS-10 prevent false NMI triggers from power supply noise?
The DS1238AS-10 implements time-domain hysteresis on the IN pin: it samples the voltage every ~33 µs using an internal ring oscillator and requires three consecutive out-of-tolerance readings (≈100 µs total) before asserting NMI. This design rejects transient spikes while preserving response to genuine slow-decay brownouts.
Can DS1238AS-10 directly power a 64k×8 SRAM during main supply loss?
Yes, DS1238AS-10's VCCO output delivers up to 100 mA at VCC−0.3 V during normal operation and sustains SRAM with VBAT−0.8 V during backup, meeting the current requirements of standard 64k×8 CMOS SRAMs. Its CEO output also enforces write protection within 144 µs of VCC decay to prevent data corruption.
Is the DS1238AS-10 pinout compatible with MAX691, and what are the functional limitations?
DS1238AS-10 is pin-for-pin compatible with MAX691 in 16-pin DIP/SOIC packages, sharing identical VCC, GND, RST, PF, and CEI/CEO pin assignments. However, DS1238AS-10 adds IN, NMI, WDS, OSCIN, OSCSEL, and RVT pins-functions absent in MAX691-so full feature parity requires board-level redesign beyond footprint reuse.
DS1238AS-10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- MicroManager
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.37V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 40ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DS1238AS-10 FAQ
1.How can I place an order for DS1238AS-10 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1238AS-10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1238AS-10 reliable?
The price and inventory of DS1238AS-10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1238AS-10 is usually 5 days.
3.What payment methods are accepted for DS1238AS-10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1238AS-10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1238AS-10?
DS1238AS-10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1238AS-10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1238AS-10?
For technical support, including DS1238AS-10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1238AS-10 requirements.
6.How does Aetrix verify that DS1238AS-10 is sourced from the original manufacturer or authorized distributors?
All DS1238AS-10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1238AS-10 meets industry standards.
7.What is the process for return or replacement of DS1238AS-10?
All DS1238AS-10 units undergo pre-shipment inspection (PSI). If there is an issue with DS1238AS-10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1238AS-10 part is unused and in its original packaging.
Return procedure for DS1238AS-10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1238AS-10 Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

