Analog Devices Inc./Maxim Integrated DS1238S-10
- Part No.:
- DS1238S-10
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
DS1238S-10.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:313
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1238S-10 from Maxim Integrated (now Analog Devices) is a microprocessor supervisory IC providing power-fail detection, watchdog reset control, non-maskable interrupt generation, SRAM backup switching, and battery-freshness sealing. It monitors +5V supply with 10% trip point (4.5V), delivers active-low/high reset outputs, supports external power switching via PF, and consumes <200 nA battery current. Used in embedded systems requiring orderly shutdown and data retention during brownouts.
For engineers reviewing the DS1238S-10 datasheet, DS1238S-10 pinout, DS1238S-10 application, or DS1238S-10 equivalent, key selection criteria include VCC trip voltage tolerance (10%), watchdog timeout configurability (internal/external clock), dual-reset polarity support, CEO-controlled SRAM write protection timing, and industrial-grade temperature option (-40°C to +85°C).
Technical Context
The DS1238S-10 integrates a bandgap voltage reference and precision comparator for accurate 5V supply monitoring with 4.37V typical trip point. Its dual-reset outputs (RST active-low, RST active-high) ensure compatibility with diverse microprocessor reset logic requirements while maintaining ≥100 ms minimum reset pulse width after power-up stabilization.
Watchdog functionality uses configurable oscillator inputs (OSCSEL/OSCIN) to support either internal ring oscillator (~30 kHz) or external clock/capacitor timing, enabling programmable timeout periods ranging from 85 ms (short period) to 2.7 s (long period). The NMI output provides early warning via user-defined voltage threshold at IN pin (1.27V internal reference), with built-in 100 µs noise immunity through triple-sampling hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Trip Point | 4.5V nominal (10% under 5V); triggers RST/RST/CEO on undervoltage for reliable microprocessor halt and memory protection. |
| Battery Current | <200 nA at VBAT=3.0V; enables multi-year SRAM data retention on coin-cell batteries without significant drain. |
| Reset Pulse Width | ≥100 ms typical after VCC rise above trip point; ensures stable power and microprocessor initialization before release. |
| Watchdog Timeout | Configurable: 85 ms (short) or 2.7 s (long) with internal clock; prevents system lockup without software intervention. |
| NMI Threshold Accuracy | 1.27V ±0.12V reference; allows precise early-warning voltage sensing via resistor divider on IN pin. |
| VCCO Output Capability | 100 mA at VCC−0.3V; powers SRAM directly during main supply operation without external regulators. |
| Operating Temperature | 0°C to +70°C standard; industrial variant DS1238S-10I supports −40°C to +85°C for harsh environments. |
Pinout & Package
DS1238S-10 is available in 16-pin SOIC (300-mil) and 16-pin DIP packages. Both share identical pin mapping and electrical characteristics.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBAT | +3V Battery Input | Provides backup power path for control logic and SRAM when VCC fails; enables nonvolatile operation. |
| VCCO | Switched SRAM Supply Output | Auto-selects between VCC and VBAT to power SRAM; diode-drop isolation prevents battery charging per UL standards. |
| VCC | +5V Primary Power Input | Main system supply input; monitored for undervoltage detection and reset generation. |
| GND | Ground Reference | Common return path for all analog and digital circuitry; critical for accurate voltage threshold comparisons. |
| PF | Power-Fail Indicator | Active-high signal used to control external MOSFETs for high-current battery switchover in large SRAM systems. |
| RVT | Reset Voltage Threshold Monitor | Open-drain output indicating VCC is below trip point; used for status feedback or external logic coordination. |
| OSCIN | Oscillator Timing Input | Accepts external clock or timing capacitor to configure watchdog and reset timing intervals. |
| OSCSEL | Oscillator Select Control | Configures internal vs. external timing source for watchdog and reset pulse generation. |
| IN | Early Warning Input | High-impedance sense node for user-defined voltage threshold; enables NMI generation prior to full VCC collapse. |
| NMI | Non-Maskable Interrupt Output | Active-low interrupt signaling impending power failure; gives firmware time to save critical state before reset. |
| ST | Strobe Input | Software-triggered watchdog reset; falling edge resets timeout counter to prevent unintended system reset. |
| CEO | Chip Enable Output | Controls SRAM write-enable; held high during VCC fail to unconditionally protect memory contents. |
| CEI | Chip Enable Input | SRAM chip enable input; CEO follows CEI during normal operation but overrides it during power failure. |
| WDS | Watchdog Status Output | Latched active-low flag indicating watchdog timeout occurred; requires ST strobe or power cycle to clear. |
| RST | Reset Output (active low) | Primary microprocessor reset signal; asserted during power-up, brownout, or watchdog timeout. |
| RST | Reset Output (active high) | Complementary reset signal for processors requiring active-high reset assertion. |
Key Features
| Feature | Design Value |
|---|---|
| Unconditional Memory Write Protection | CEO forces SRAM into write-protected mode within 44 µs of VCC falling below trip point, preventing data corruption during power loss. |
| Delay-Controlled Write Protection | Hold-off time tCE (5 µs max) delays CEO assertion until current memory cycle completes, ensuring atomic data writes. |
| Freshness Seal Mode | Three negative pulses on IN pin disable VCCO/RST/CEO outputs during storage, preserving battery capacity until first power-up. |
| Pushbutton Reset Debounce | Internal RC network eliminates mechanical switch bounce on RST pin, eliminating need for external debounce components. |
| External Power Switching Support | PF output drives external MOSFETs to handle >100 mA SRAM loads, extending battery life and reducing thermal stress on IC. |
Applications
| Industrial Data Logger | Medical Diagnostic Device |
|---|---|
Use Scenario: Continuous sensor data acquisition in remote field deployments with intermittent AC power and backup battery. IC Role / Device Role / Timing Role: Supervisory controller managing power sequencing, brownout response, and SRAM data retention during grid outages. Use Value: Prevents loss of critical waveform or calibration data by triggering NMI 100 µs before VCC collapse and asserting CEO within 44 µs to lock memory. | Use Scenario: Portable ultrasound or ECG unit requiring guaranteed data integrity during battery swaps or sudden discharge events. IC Role / Device Role / Timing Role: Dual-role supervisor: provides early-warning NMI for firmware-initiated safe shutdown and unconditional CEO write protection on final VCC decay. Use Value: Enables deterministic 2.7 s watchdog timeout to recover hung firmware, while freshness seal preserves battery charge during 2-year shelf life. |
| Point-of-Sale Terminal | Smart Energy Meter |
Use Scenario: Transaction-critical retail terminal operating on mains power with supercapacitor backup for last-transaction commit. IC Role / Device Role / Timing Role: Power-fail coordinator generating synchronized RST (active-low) and RST (active-high) to halt CPU and latch transaction state in SRAM. Use Value: 100 ms minimum reset pulse ensures complete CPU shutdown before VCC drops below 4.25V, avoiding partial instruction execution. | Use Scenario: Utility meter with tamper-proof nonvolatile storage for billing records and firmware logs across decades of operation. IC Role / Device Role / Timing Role: Long-term SRAM guardian using VBAT-backed VCCO and CEO-controlled write protection to maintain 10+ year data retention. Use Value: <200 nA battery current extends CR2032 life beyond 10 years; PF output controls external load switch for >500 mA backup loads. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691CPD+ | Pin-compatible legacy part; same 10% VCC trip (4.5V), but lacks freshness seal and has higher 1 µA battery current. | No built-in NMI early-warning path; requires external comparator for pre-fail notification. | Select MAX691CPD+ only if legacy design reuse is required and freshness seal/NMI are not needed. |
| TPS3823-50DBVR | Dedicated supervisor with 5% VCC threshold (4.75V); no NMI, no CEO, no watchdog, no battery backup switching. | Single-function reset generator only; cannot replace DS1238S-10's integrated SRAM management or early-warning capability. | Choose TPS3823-50DBVR only for simple reset-only applications where SRAM backup and NMI are handled separately. |
Compared with MAX691CPD+, DS1238S-10 adds freshness seal, lower battery drain, and NMI-critical for long-life portable devices. Versus TPS3823-50DBVR, DS1238S-10 integrates power switching, memory control, and watchdog, eliminating 3–4 discrete components in battery-backed systems.
Availability
DS1238S-10 is available at Aetrix Electronics and suitable for industrial data loggers, medical diagnostic devices, point-of-sale terminals, and smart energy meters requiring stable component supply and long-term lifecycle support.
Supply support for DS1238S-10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (via acquisition of Maxim Integrated) designs precision analog, mixed-signal, and power management ICs for high-reliability industrial, automotive, and medical applications.
The DS1238S-10 belongs to Maxim's MicroManager family of supervisory ICs, engineered specifically for microprocessor-based systems needing coordinated power monitoring, reset control, and nonvolatile memory backup in space-constrained designs.
FAQ
What is the exact VCC trip voltage specification for DS1238S-10?
The DS1238S-10 has a nominal VCC trip point of 4.5V (10% below 5V), with a typical value of 4.37V and a guaranteed range of 4.25V to 4.50V across temperature and process variation. This threshold triggers RST, RST, RVT, and CEO actions simultaneously to ensure deterministic system response during brownout conditions.
Does DS1238S-10 support both active-low and active-high reset outputs?
Yes, DS1238S-10 provides two independent reset outputs: RST (active-low) and RST (active-high), both asserted simultaneously during power-up, VCC undervoltage, or watchdog timeout. This dual-polarity capability eliminates level-shifting requirements for microprocessors with differing reset input logic conventions.
How does the DS1238S-10 implement early warning of power failure?
The DS1238S-10 uses its IN pin and internal 1.27V reference to generate an NMI signal when a user-defined voltage threshold is crossed. With built-in triple-sampling hysteresis, it requires ~100 µs of sustained undervoltage to assert NMI-rejecting noise while delivering actionable early warning before VCC reaches the 4.5V reset threshold.
Can DS1238S-10 directly power SRAM during battery backup?
Yes, DS1238S-10 supplies up to 1 mA through VCCO during battery operation (VBAT mode), sufficient for low-power CMOS SRAMs. Its internal power switch automatically selects VCC or VBAT, and CEO output disables SRAM writes when VCC falls below 4.5V-ensuring data integrity without external logic.
What is the purpose of the freshness seal function in DS1238S-10?
DS1238S-10's freshness seal electrically disconnects the battery during storage by tri-stating VCCO, RST, RST, and CEO outputs. Activated by three negative pulses on IN, it preserves battery capacity for up to 10+ years-critical for field-deployed equipment with long shelf life before first use.
DS1238S-10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- MicroManager
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.37V
- Output:
- Open Drain, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- 40ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DS1238S-10 FAQ
1.How can I place an order for DS1238S-10 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1238S-10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1238S-10 reliable?
The price and inventory of DS1238S-10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1238S-10 is usually 5 days.
3.What payment methods are accepted for DS1238S-10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1238S-10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1238S-10?
DS1238S-10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1238S-10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1238S-10?
For technical support, including DS1238S-10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1238S-10 requirements.
6.How does Aetrix verify that DS1238S-10 is sourced from the original manufacturer or authorized distributors?
All DS1238S-10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1238S-10 meets industry standards.
7.What is the process for return or replacement of DS1238S-10?
All DS1238S-10 units undergo pre-shipment inspection (PSI). If there is an issue with DS1238S-10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1238S-10 part is unused and in its original packaging.
Return procedure for DS1238S-10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1238S-10 Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

