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Analog Devices Inc./Maxim Integrated DS1238S-5/T&R
- Part No.:
- DS1238S-5/T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
DS1238S-5/T&R.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:675
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Product details
Overview
DS1238S-5/T&R from Maxim Integrated (now Analog Devices) is a microprocessor supervisory IC providing power-fail detection, watchdog timer, non-maskable interrupt, and SRAM battery backup control in 5V systems. It features 4.5V ±10% VCC trip point, 200nA battery current, dual active-low/active-high reset outputs, and pin-compatible replacement for MAX691. Used in industrial controllers requiring orderly shutdown during brownout.
For engineers reviewing the DS1238S-5/T&R datasheet, DS1238S-5/T&R pinout, DS1238S-5/T&R application, or DS1238S-5/T&R equivalent, key selection criteria include reset timeout duration, VCC trip accuracy, NMI early-warning threshold, watchdog timing flexibility via OSCSEL/OSCIN, and SRAM write-protection sequencing with CEI/CEO handshaking.
Technical Context
The DS1238S-5/T&R integrates a bandgap voltage reference and precision comparator to monitor VCC against a 4.5V nominal trip point (±10%), triggering RST/RST and RVT within 175µs. Its watchdog timer supports internal (2.7s typical) or external clock sources via OSCSEL/OSCIN, with ST strobe input resetting on high-to-low transition.
Early warning is implemented via high-impedance IN pin referenced to 1.27V internal threshold, requiring three consecutive 33µs samplings below VTP to assert NMI - eliminating noise-induced false triggers. Memory backup uses VCCO switching between VCC and VBAT, with CEO write-protection delayed until CEI returns high or tCE (5µs) expires.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Trip Point | 4.5V ±10% (4.37V typical); ensures reset activation before microprocessor operational failure. |
| Battery Current (IBAT) | <200 nA at VBAT=3.0V; enables multi-year SRAM data retention on coin cell. |
| Reset Timeout (tRST) | 40–150 ms after VCC rise above trip point; provides stable power-up delay for CPU initialization. |
| Watchdog Timeout | 2.7 s typical (internal clock); configurable to 170 ms or external clock cycles for software supervision granularity. |
| NMI Assertion Delay (tIPD) | 40–175 µs from IN voltage drop below 1.27V; delivers deterministic early warning before VCC collapse. |
| CEO Propagation Delay | 20 ns max; guarantees fast SRAM write-protection activation upon power failure detection. |
| VCCO Output Capability | 100 mA at VCC−0.3V; powers SRAM directly without external regulators in compact designs. |
Pinout & Package
DS1238S-5/T&R is supplied in 16-pin SOIC (300-mil) package, RoHS-compliant, tape-and-reel format (T&R). Pinout matches 16-pin DIP variant electrically; no thermal pad or exposed die attach.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBAT | +3V Battery Input | Provides backup power path for control logic and SRAM when VCC fails; diode-isolated to prevent battery charging. |
| VCCO | Switched SRAM Supply Output | Auto-selects higher of VCC or VBAT to power SRAM; drops to VBAT−0.8V under load to meet UL safety limits. |
| VCC | +5V Primary Power Input | Main system supply input; monitored for out-of-tolerance condition triggering reset and memory protection. |
| GND | System Ground Reference | Common return for all analog and digital functions; critical for accurate voltage threshold comparison. |
| PF | Power-Fail Indicator (active high) | Drives external MOSFET or PMIC to switch load from VCC to VBAT; transitions within 2µs of VBAT detection. |
| RVT | Reset Voltage Threshold Monitor | Open-drain output indicating VCC has fallen below trip point; used for system-level power status logging. |
| OSCIN | Oscillator Timing Input/Capacitor Node | Accepts external capacitor (e.g., 47pF) or clock signal to set watchdog and reset timing intervals. |
| OSCSEL | Oscillator Select Control | Configures internal vs. external clock source; tri-stated when VCC < VBAT to disable timing during battery-only operation. |
| IN | Early Warning Input | High-impedance sense node for user-defined voltage divider; triggers NMI when input falls below 1.27V. |
| NMI | Non-Maskable Interrupt Output | Active-low interrupt signaling imminent power loss; synchronized to internal 30kHz sampling to reject noise. |
| ST | Watchdog Strobe Input | High-to-low edge resets watchdog timer; must occur before timeout to prevent forced reset. |
| CEO | Chip Enable Output | Write-protects SRAM by forcing CE high; delayed until CEI returns high or 5µs tCE expires to complete memory cycle. |
| CEI | Chip Enable Input | SRAM chip enable input; CEO follows CEI with 20ns delay during normal operation. |
| WDS | Watchdog Status Output | Latched active-low flag indicating watchdog timeout occurred; cleared only by ST strobe or VCC recovery. |
| RST | Reset Output (active low) | Primary microprocessor reset signal; held active ≥40ms after VCC rises above trip point. |
| RST | Reset Output (active high) | Complementary reset signal for systems requiring active-high assertion; identical timing to RST. |
Key Features
| Feature | Design Value |
|---|---|
| Unconditional SRAM Write Protection | CEO forces SRAM CE high within 44µs of VCC falling below trip point, preventing data corruption during power loss. |
| Programmable Watchdog Timing | Three timeout options (2.7s/170ms/110ms) selectable via OSCSEL and OSCIN capacitor value - no firmware changes needed. |
| Noise-Immune Early Warning | NMI requires three consecutive 33µs samples below 1.27V at IN pin, rejecting transients <100µs duration. |
| Freshness Seal Mode | Tri-states VCCO, RST, RST, and CEO during storage using three negative pulses on IN - preserves battery capacity pre-deployment. |
| Pushbutton Reset Debounce | Internal RC network eliminates mechanical switch bounce on RST pin, eliminating need for external RC components. |
Applications
| Industrial PLC Controller | Medical Diagnostic Equipment |
|---|---|
Use Scenario: Programmable logic controller operating in factory environments with unstable AC line input. IC Role / Device Role / Timing Role: Supervisory IC monitoring 5V rail, asserting NMI for controlled I/O state freeze and RST for safe CPU halt before brownout. Use Value: Prevents corrupted ladder logic execution and ensures deterministic shutdown sequence compliant with IEC 61131-2. | Use Scenario: Portable ultrasound machine requiring persistent calibration data storage during battery swaps. IC Role / Device Role / Timing Role: SRAM backup controller managing VCCO switchover and CEO write-protection timing during VCC interruption. Use Value: Guarantees zero-data-loss SRAM retention for 10+ years on CR2032 via <200nA IBAT and VBAT isolation. |
| Telecom Base Station Shelf | Energy Meter with Tamper Detection |
Use Scenario: Remote radio unit powered by PoE with transient surges from lightning-induced ground shifts. IC Role / Device Role / Timing Role: Power supervisor detecting 5V droop, driving PF to engage backup DC-DC converter before VCC collapse. Use Value: Enables seamless failover to secondary power within 2µs, maintaining 1588 PTP time sync without packet loss. | Use Scenario: Smart electricity meter subjected to intentional power cycling attacks. IC Role / Device Role / Timing Role: Watchdog and reset manager verifying firmware integrity via ST strobe; triggers RST if ST stalls >2.7s. Use Value: Detects malicious firmware lockup and forces secure boot recovery, meeting ANSI C12.10 tamper-evidence requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691CPD+ | Identical pinout and core functionality; 4.65V trip point (±2.5%) vs. DS1238S-5's 4.5V (±10%); no freshness seal mode. | Used in legacy designs where tighter trip tolerance is required but battery conservation during storage is not critical. | Select MAX691CPD+ when absolute VCC threshold accuracy outweighs ultra-low IBAT and freshness seal needs. |
| TPS3823-50DBVR | Single active-low reset output; fixed 4.63V trip; no NMI, watchdog, or SRAM control; 1.6µA quiescent current (vs. 4mA ICC). | Suitable for simple reset-only applications where early warning, memory backup, and watchdog are unnecessary. | Choose TPS3823-50DBVR only for cost-sensitive, low-feature-count systems lacking SRAM or NMI requirements. |
Compared with MAX691CPD+, DS1238S-5/T&R offers lower battery drain and storage-mode freshness seal; versus TPS3823-50DBVR, it delivers full supervisory functionality - NMI, watchdog, CEO handshaking, and dual-reset outputs - at the cost of higher active current.
Availability
DS1238S-5/T&R is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, telecom infrastructure, and smart metering applications requiring stable component supply and long-term obsolescence management.
Supply support for DS1238S-5/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (formerly Maxim Integrated) designs precision analog, mixed-signal, and power management ICs for high-reliability industrial, automotive, and communications systems.
The DS1238S-5/T&R belongs to Maxim's MicroManager family - engineered specifically for robust power supervision, orderly microprocessor shutdown, and nonvolatile SRAM backup in mission-critical embedded systems.
FAQ
What is the exact VCC trip point specification for DS1238S-5/T&R?
The DS1238S-5/T&R has a nominal VCC trip point of 4.5V with ±10% tolerance (4.25V to 4.50V), yielding a typical value of 4.37V. This is confirmed in the DC Electrical Characteristics table (page 12) and distinguishes it from the DS1238-5 variant, which uses a 5% tolerance (4.75V trip). The trip point is set by an internal bandgap reference and comparator, ensuring consistent behavior across temperature and supply variations. DS1238S-5/T&R maintains this specification in its 16-pin SOIC package under commercial temperature range (0°C to +70°C).
Does DS1238S-5/T&R support both active-low and active-high reset outputs simultaneously?
Yes, DS1238S-5/T&R provides two independent reset outputs: RST (active low) and RST (active high), both asserted simultaneously when VCC falls below the trip point or watchdog times out. Their timing is synchronized - both remain active for 40–150 ms after VCC rises above the trip point (tRPU), with propagation delays under 175µs from fault detection. This dual-output capability eliminates need for external inverters in systems requiring either polarity, and is explicitly documented in the PIN ASSIGNMENT and AC Electrical Characteristics sections of the datasheet.
How does the DS1238S-5/T&R implement early warning power-fail detection?
The DS1238S-5/T&R implements early warning via the IN pin and NMI output: a precision comparator monitors voltage at IN relative to a 1.27V internal reference (VTP = 1.15V to 1.35V). When IN falls below VTP, the device asserts NMI only after three consecutive 33µs samplings confirm the condition - rejecting noise spikes shorter than ~100µs. This mechanism is detailed in the NON-MASKABLE INTERRUPT section (pages 4–5). DS1238S-5/T&R requires no external components beyond a resistor divider to scale higher supply voltages to the IN pin, making it adaptable to 5V, 12V, or other rails.
Can DS1238S-5/T&R be used to back up external SRAM without additional discrete components?
Yes, DS1238S-5/T&R integrates all necessary functions for SRAM backup: VCCO automatically selects the higher of VCC or VBAT to power the SRAM, while CEO provides write-protection control. CEO is unconditionally driven high within 44µs of VCC failure (tCF), but delays activation until CEI returns high or 5µs (tCE) elapses - ensuring current memory cycle completes. This eliminates need for external diodes, MOSFETs, or glue logic. The DS1238S-5/T&R datasheet confirms this in the MEMORY BACKUP section (page 7) and Figure 7 (NONVOLATILE SRAM).
What is the purpose and activation method of the freshness seal mode in DS1238S-5/T&R?
The freshness seal mode in DS1238S-5/T&R conserves battery capacity during storage by electrically disconnecting VBAT from internal circuitry. It is activated by applying three precise negative pulses (0V to −3V) to the IN pin while VCC is at +5V - a sequence defined in Figure 8. Once engaged, VCCO, RST, RST, and CEO enter high-impedance state, and WDS goes active low. Normal operation resumes only after VCC is cycled above VBAT. This feature is unique to the DS1238 family and is absent in pin-compatible alternatives like MAX691. DS1238S-5/T&R supports this mode in both SOIC and DIP packages.
DS1238S-5/T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- MicroManager
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.62V
- Output:
- Open Drain, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- 40ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DS1238S-5/T&R FAQ
1.How can I place an order for DS1238S-5/T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1238S-5/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1238S-5/T&R reliable?
The price and inventory of DS1238S-5/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1238S-5/T&R is usually 5 days.
3.What payment methods are accepted for DS1238S-5/T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1238S-5/T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1238S-5/T&R?
DS1238S-5/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1238S-5/T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1238S-5/T&R?
For technical support, including DS1238S-5/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1238S-5/T&R requirements.
6.How does Aetrix verify that DS1238S-5/T&R is sourced from the original manufacturer or authorized distributors?
All DS1238S-5/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1238S-5/T&R meets industry standards.
7.What is the process for return or replacement of DS1238S-5/T&R?
All DS1238S-5/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1238S-5/T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1238S-5/T&R part is unused and in its original packaging.
Return procedure for DS1238S-5/T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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