Analog Devices Inc./Maxim Integrated DS1239-10+
- Part No.:
- DS1239-10+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
DS1239-10+.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:498
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1239-10+ from Maxim Integrated (now Analog Devices) is a microprocessor supervisory IC that provides power-up/down sequencing, reset generation, nonvolatile SRAM backup control, and power-fail warning in embedded systems. It features 10% VCC monitoring accuracy, active-low RST output, dual PF outputs (active-high and active-low), and supports battery-backed memory write-protection at VCC out-of-tolerance. Used in industrial controllers requiring orderly shutdown during brownout.
For engineers reviewing the DS1239-10+ datasheet, DS1239-10+ pinout, DS1239-10+ application, or DS1239-10+ equivalent, key selection criteria include its PSI/PSO power-control interface, dual PF signaling, VBAT-powered NMI assertion during power failure, WC/SC sleep/wake capability, and compatibility with DS1236-based designs requiring NMOS-mode timing and pin mapping.
Technical Context
The DS1239-10+ implements a dedicated power-supply control architecture using PSI (input) and PSO (output) to initiate AC-to-DC power-up via opto-SCR triggering, with tPSI = 200 ms minimum turn-on response and tPSP = 200–500 ms pulse width. It retains full functional equivalence to the DS1236 in NMOS mode except for RC→PSI and RST→PSO pin reassignments.
It monitors +5V supply (VCC) with ±10% threshold accuracy, asserts active-low RST during power transients, generates early-warning IN signal before PF, and unconditionally write-protects SRAM when VCC falls outside tolerance - all while consuming <100 nA from VBAT. The dual PF pins support both active-high and active-low interrupt logic for host microprocessor interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Monitoring Accuracy | ±10% - ensures reliable reset assertion across manufacturing and temperature variation without external trimming |
| RST Output Polarity | Active-low - directly interfaces with standard microprocessor reset inputs requiring low-level assertion |
| PSI Input Current | 3 µA max - enables direct connection to keypad matrix or pushbutton with 0.1 µF debounce capacitor |
| PSO Output Drive | 10 mA sink/source - sufficient to drive opto-SCR gate for AC power switch control without buffer stage |
| VBAT Current Draw | <100 nA - extends 3V lithium battery life to >10 years in standby memory backup applications |
| Operating Temp Range | 0°C to +70°C - qualified for commercial-grade embedded control and instrumentation environments |
| tPSI Response Time | 200 ms min - guarantees minimum hold time for reliable AC power supply startup sequencing |
Pinout & Package
DS1239-10+ is available in 16-pin plastic DIP (300-mil) and 16-pin SOIC (300-mil) packages. Both share identical pin mapping and thermal characteristics.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBAT | Battery input | Provides backup power for NMI, PF, and memory protection logic when VCC fails |
| VCCO | Switched SRAM supply | Delivers VCC to SRAM only when system is powered and stable; disconnects during reset or power loss |
| VCC | +5V main supply input | Primary power source; monitored for out-of-tolerance condition to trigger RST and write-protect |
| GND | Ground reference | Common return path for all analog and digital functions; decoupling required near VCC/GND pair |
| PF (pin 5 & 6) | Power-fail indicator | Dual outputs: one active-high, one active-low - supports interrupt logic on either polarity microcontroller |
| WC/SC | Sleep/wake control | Enables low-power "stop mode" in handheld devices by halting CPU clock and preserving SRAM state |
| PSI | Power-start input | Edge-triggered input initiating AC power-up sequence; internally pulled high by VBAT |
| PSO | Power-switch output | Drives opto-SCR gate; sources up to 10 mA for 200–500 ms to ensure reliable power supply turn-on |
| RST | Reset output | Active-low open-drain output asserting microprocessor reset during power transients or brownout |
| PBRST | Pushbutton reset input | Debounced hardware reset initiation independent of power supply status |
| NMI | Non-maskable interrupt | Asserted on VCC drop to warn CPU of imminent power failure before RST activates |
| IN | Early warning input | Allows external circuit to preemptively signal power degradation before PF activation |
| CEO / CEI | Chip enable chain | Supports daisy-chained memory backup control across multiple DS1239 units |
| ST | Strobe input | Used to latch internal status during power transition for diagnostic logging |
Key Features
| Feature | Design Value |
|---|---|
| PSI/PSO power sequencing interface | Eliminates need for external AC power switch controller; enables keyboard-initiated soft power-on/off |
| Dual PF outputs (active-high & active-low) | Removes level-shifter requirement for interrupt routing to diverse microcontroller families |
| Unconditional SRAM write-protection | Prevents data corruption during power collapse by disabling write strobes before VCC drops below safe margin |
| VCC monitoring with ±10% accuracy | Meets MIL-STD-704 and IEC 61000-4-11 immunity thresholds for brownout detection |
| Sub-100 nA VBAT quiescent current | Permits use of coin-cell batteries for >10-year nonvolatile memory retention without replacement |
Applications
| Industrial PLC Controller | Medical Infusion Pump |
|---|---|
Use Scenario: Maintains real-time dosage history in SRAM during AC mains interruption or battery switchover. IC Role / Device Role / Timing Role: DS1239-10+ asserts NMI at first sign of VCC sag, triggers controlled save-to-EEPROM, then asserts RST after safe shutdown window. Use Value: Prevents therapy interruption and ensures audit-trail integrity under 100-ms brownouts per IEC 60601-1 clause 15.3.2. | Use Scenario: Enables zero-power "standby" mode between infusion cycles while preserving calibration and patient settings. IC Role / Device Role / Timing Role: DS1239-10+ monitors VCC and uses WC/SC to halt CPU clock; VCCO remains active to retain SRAM contents. Use Value: Reduces average system power from 120 mW to 1.8 µW, extending AA battery life from 3 to 18 months. |
| Point-of-Sale Terminal | Energy Meter Data Logger |
Use Scenario: Safeguards transaction log during unexpected AC dropout during credit card processing. IC Role / Device Role / Timing Role: DS1239-10+ detects VCC decay, asserts PF to initiate flash write, then disables VCCO to freeze SRAM until power resumes. Use Value: Guarantees atomic commit of last transaction even during sub-50-ms interruptions per EMVCo v4.3 section 7.2.1. | Use Scenario: Preserves 30-day consumption history in battery-backed SRAM during grid outage or meter replacement. IC Role / Device Role / Timing Role: DS1239-10+ uses CEO/CEI chaining to coordinate backup across multiple memory banks during extended VCC loss. Use Value: Eliminates need for EEPROM wear leveling; supports 100,000+ power-cycle endurance without data loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1239-5+ | 5% VCC monitoring accuracy vs. 10% - tighter threshold improves noise immunity but increases cost | Required where brownout detection must distinguish between 4.75V and 4.85V supply dips | Select DS1239-5+ only if design requires <±5% VCC tolerance per JEDEC JESD8-12E |
| MAX690TSA+ | Single PF output (active-low only); no PSI/PSO interface; includes watchdog timer not present in DS1239-10+ | Used in simpler systems lacking keyboard-controlled power sequencing | Choose MAX690TSA+ when watchdog supervision is needed and AC power control is handled externally |
Compared with DS1239-5+, the DS1239-10+ trades tighter voltage monitoring for lower cost and broader noise margin; compared with MAX690TSA+, it offers unique PSI/PSO sequencing but lacks watchdog functionality - making DS1239-10+ optimal for keyboard-initiated power management in legacy NMOS-mode systems.
Availability
DS1239-10+ is available at Aetrix Electronics and suitable for industrial PLC controllers, medical infusion pumps, point-of-sale terminals, and energy meter data loggers requiring stable component supply and long-term obsolescence support.
Supply support for DS1239-10+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (via acquisition of Maxim Integrated) designs precision analog, mixed-signal, and power management ICs for industrial, automotive, and communications infrastructure.
The DS1239-10+ belongs to Maxim's MicroManager family - engineered specifically for robust power sequencing, nonvolatile memory backup, and fail-safe reset control in microprocessor systems operating from AC/DC or battery hybrid supplies.
FAQ
What is the primary function of the DS1239-10+ in a microprocessor system?
The DS1239-10+ serves as a dedicated supervisory IC that manages power-up/down sequencing, generates reset signals, protects battery-backed SRAM during power loss, and warns the microprocessor of impending power failure. Its PSI/PSO interface enables keyboard-initiated AC power control, and its dual PF outputs support both active-high and active-low interrupt logic - all critical functions implemented within the DS1239-10+ without external components.
How does the DS1239-10+ differ from the DS1236?
The DS1239-10+ is functionally identical to the DS1236 in NMOS mode except for two pin replacements: RC is renamed PSI, and RST is replaced by PSO. All other pins, timing, and electrical behavior match the DS1236. This change enables direct integration into power-control architectures requiring active switching of external AC power supplies - a capability not supported by the original DS1236's RC/RST configuration.
What is the purpose of the WC/SC pin on the DS1239-10+?
The WC/SC (Wake-Up Control/Sleep Control) pin on the DS1239-10+ enables low-power "stop mode" operation in battery-powered handheld devices. When asserted, it halts the microprocessor clock while maintaining VCCO to preserve SRAM contents. Upon wake-up signal, the DS1239-10+ restores full operation - allowing systems like portable medical instruments to achieve µA-level standby current without losing volatile context.
Does the DS1239-10+ support industrial temperature range?
The DS1239-10+ is specified for 0°C to +70°C operation. An industrial-grade variant designated DS1239-10IND+ supports –40°C to +85°C, but the DS1239-10+ itself is not rated for extended temperature. Designs requiring industrial operation must verify thermal derating or select the IND version - the DS1239-10+ datasheet explicitly limits ambient operating range to commercial grade.
Can the DS1239-10+ be used to convert standard SRAM into nonvolatile memory?
Yes - the DS1239-10+ converts CMOS SRAM into nonvolatile memory by controlling VCCO (switched SRAM supply) and asserting unconditional write-protection when VCC falls out of tolerance. During power loss, it disconnects VCCO and disables write enables, preserving SRAM data powered solely by VBAT. This architecture is validated in DS1239-10+ applications including energy meters and medical loggers where data retention exceeds 10 years on a single CR2032 cell.
DS1239-10+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- MicroManager
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.37V
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 25ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
DS1239-10+ FAQ
1.How can I place an order for DS1239-10+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1239-10+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1239-10+ reliable?
The price and inventory of DS1239-10+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1239-10+ is usually 5 days.
3.What payment methods are accepted for DS1239-10+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1239-10+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1239-10+?
DS1239-10+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1239-10+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1239-10+?
For technical support, including DS1239-10+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1239-10+ requirements.
6.How does Aetrix verify that DS1239-10+ is sourced from the original manufacturer or authorized distributors?
All DS1239-10+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1239-10+ meets industry standards.
7.What is the process for return or replacement of DS1239-10+?
All DS1239-10+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1239-10+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1239-10+ part is unused and in its original packaging.
Return procedure for DS1239-10+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1239-10+ Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

