Analog Devices Inc./Maxim Integrated DS1267S-010/T&R

Overview

DS1267S-010/T&R from Maxim Integrated (now Analog Devices) is a dual-channel, 256-position digital potentiometer in 16-pin SOIC package with 10 kΩ end-to-end resistance per channel, ±0.3 LSB relative linearity, and 3-wire serial interface (RST/CLK/DQ). It operates from 4.5–5.5 V over -40°C to +85°C and supports stacked configuration for 512-step resolution in precision gain control and offset adjustment circuits.

For engineers reviewing the DS1267S-010/T&R datasheet, DS1267S-010/T&R pinout, DS1267S-010/T&R application, or DS1267S-010/T&R equivalent, key selection considerations include wiper resistance (400–1000 Ω), standby current (22 µA), cascade capability via COUT/DQ daisy-chaining, and industrial temperature range compliance.

Technical Context

The DS1267S-010/T&R integrates two independent 8-bit-controlled resistive arrays, each with 256 tap points and temperature-compensated thin-film elements. Its 3-wire serial interface uses RST as chip-select enable, CLK for synchronous bit transfer, and DQ for bidirectional data flow - supporting both write (wiper position + stack select bit) and read-back via COUT feedback.

Stacked mode connects H1–L0 internally to double total resistance to 20 kΩ and extend resolution to 9 bits; cascade operation chains multiple DS1267S-010/T&R devices using COUT-to-DQ routing with 50 ns propagation delay, enabling single-processor control of up to 16 units without additional I/O pins.

Key Specifications

Pinout & Package

DS1267S-010/T&R is housed in a 16-pin SOIC (300-mil) package with gull-wing leads, 1.27 mm pitch, and JEDEC MS-012AC compliant footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual digital potentiometer applications.

Compared with AD5232BRUZ10 and MCP42010-I/P, DS1267S-010/T&R uniquely supports hardware stacking (512-step resolution) and daisy-chain cascading via COUT - critical for space-constrained multi-pot systems where EEPROM overhead or SPI pin count is prohibitive.

Availability

DS1267S-010/T&R is available at Aetrix Electronics and suitable for industrial instrumentation, sensor calibration, and programmable analog front-ends requiring stable component supply, long-lifecycle assurance, and traceable sourcing.

Supply support for DS1267S-010/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (acquired by Analog Devices in 2021) designs precision analog, mixed-signal, and power management ICs for industrial, medical, and communications markets.

The DS1267S-010/T&R belongs to Maxim's digital potentiometer family engineered for high-accuracy, low-power analog trimming in harsh-temperature environments - emphasizing linearity, cascade scalability, and minimal external component count.

FAQ

What is the function of the VB pin on the DS1267S-010/T&R?

The VB (substrate bias) pin on the DS1267S-010/T&R must be connected to GND for normal operation. It provides a reference for the internal CMOS switches controlling the resistive array; leaving VB floating or applying incorrect voltage causes undefined wiper behavior and potential damage. The datasheet specifies VB = GND as the only valid condition for 10 kΩ operation.

Can the DS1267S-010/T&R operate from a 3.3 V supply?

No, the DS1267S-010/T&R is specified only for 4.5–5.5 V operation per its Recommended DC Operating Conditions. At 3.3 V, the internal logic levels (VIH ≥ 2.0 V, VIL ≤ 0.8 V) and analog switch thresholds become unreliable, resulting in failed serial communication and erratic wiper positioning. Use AD5232 or MCP42XX series for true 3.3 V compatibility.

How does the stacked configuration affect total resistance and resolution in the DS1267S-010/T&R?

In stacked mode, DS1267S-010/T&R connects H1 to L0 internally, yielding 20 kΩ total end-to-end resistance and 512 distinct wiper positions (9-bit effective resolution). The SOUT pin outputs either W0 or W1 based on the stack select bit (bit 0 of the 17-bit shift register), enabling seamless extension of range without external wiring.

Is the DS1267S-010/T&R pin-compatible with other DS1267 variants like DS1267S-050?

Yes - all DS1267S-x variants (010, 050, 100) share identical 16-pin SOIC pinout, electrical interface, and timing. Only the end-to-end resistance differs (10 kΩ vs. 50 kΩ vs. 100 kΩ); substituting DS1267S-010/T&R for DS1267S-050 requires verifying that 10 kΩ meets circuit gain/attenuation requirements and that wiper resistance impact remains acceptable.

What is the maximum number of DS1267S-010/T&R devices that can be cascaded reliably?

The DS1267S-010/T&R supports daisy-chaining up to 16 units with guaranteed timing integrity, as confirmed by the 50 ns COUT propagation delay and AC Electrical Characteristics table. Beyond 16, clock skew and cumulative delay may violate tDC (30 ns min data setup) and tCDH (10 ns min hold) requirements - verify signal integrity with scope measurements for larger chains.