Analog Devices Inc./Maxim Integrated DS1267S-100/T&R

Overview

DS1267S-100/T&R from Maxim Integrated (now Analog Devices) is a dual-channel, 256-position digital potentiometer in 16-pin SOIC package with 100 kΩ end-to-end resistance per channel, ±0.3 LSB relative linearity, and 3-wire serial interface (RST/CLK/DQ). It operates from 4.5–5.5 V at -40°C to +85°C and supports stacked configuration for 512-step resolution in precision analog gain/attenuation circuits.

For engineers reviewing the DS1267S-100/T&R datasheet, DS1267S-100/T&R pinout, DS1267S-100/T&R application, or DS1267S-100/T&R equivalent, key selection considerations include wiper resistance (400–1000 Ω), standby current (22 µA), cascade daisy-chaining capability via COUT/DQ, and industrial temperature-rated operation without external charge pumps.

Technical Context

The DS1267S-100/T&R integrates two independent 8-bit-controlled resistive arrays, each with 256 tap points and temperature-compensated thin-film elements. Its 3-wire serial interface uses RST as chip-select enable, CLK for synchronous bit transfer, and DQ for bidirectional data flow into a 17-bit shift register holding two wiper positions and a stack-select bit.

Stacked mode connects both potentiometers in series via H0–L1 routing, doubling total resistance to 200 kΩ and enabling 9-bit (512-step) resolution with SOUT selecting W0 or W1 output based on bit-0 of the shift register. Cascading is supported through COUT-to-DQ daisy chaining with ≤50 ns propagation delay and no RST dependency for read-through feedback.

Key Specifications

Pinout & Package

16-pin SOIC (300-mil) surface-mount package with standard JEDEC outline; body width 3.9 mm, lead pitch 1.27 mm, thermal pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual digital potentiometer applications.

Compared with AD5232BRUZ100 and MCP42100-I/SL, the DS1267S-100/T&R uniquely supports daisy-chain cascading and stacked-series configuration while delivering superior ±0.3 LSB relative linearity - making it optimal for multi-channel synchronized analog control where resolution and monotonicity are critical.

Availability

DS1267S-100/T&R is available at Aetrix Electronics and suitable for industrial automation, test and measurement instrumentation, and medical analog front-end design requiring stable component supply, long-lifecycle availability, and traceable sourcing.

Supply support for DS1267S-100/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (acquired by Analog Devices in 2021) is a U.S.-based semiconductor company specializing in precision analog, mixed-signal, and high-reliability ICs for industrial, automotive, and communications markets.

The DS1267S-100/T&R belongs to Maxim's digital potentiometer product line, designed specifically for replacing mechanical trimmers in programmable analog signal conditioning systems with guaranteed linearity, low power, and robust serial control.

FAQ

What is the function of the VB pin on the DS1267S-100/T&R?

The VB (substrate bias) pin on the DS1267S-100/T&R must be connected to GND for normal operation. It provides substrate bias control for the internal CMOS switches and resistive elements. Leaving VB floating or applying incorrect voltage violates absolute maximum ratings and may cause latch-up or parametric failure. The DS1267S-100/T&R datasheet specifies VB = GND as the recommended condition for all standard applications.

Does the DS1267S-100/T&R retain wiper settings after power cycling?

No, the DS1267S-100/T&R is a volatile digital potentiometer: wiper positions reset to mid-scale (128 decimal, 50% resistance) on power-up. It does not contain EEPROM or nonvolatile memory. To maintain a specific setting across power cycles, the host microcontroller must reinitialize the DS1267S-100/T&R via its 3-wire interface during startup sequence.

Can the DS1267S-100/T&R be used in a single-supply 3.3 V system?

No - the DS1267S-100/T&R is specified only for 4.5 V to 5.5 V operation per its Recommended DC Operating Conditions. At 3.3 V, logic thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V) become marginal, and internal switch performance degrades. Attempting 3.3 V operation risks communication failure, increased wiper resistance, and violation of absolute maximum ratings on resistor pins.

How does the stacked configuration work on the DS1267S-100/T&R?

In stacked configuration, the DS1267S-100/T&R connects Potentiometer-0 (H0–L0) and Potentiometer-1 (H1–L1) in series via external PCB routing (H0 to L1), yielding 200 kΩ total resistance. The SOUT pin outputs either W0 or W1 based on the stack-select bit (bit-0 of the 17-bit shift register), enabling 512-step resolution while retaining independent control of each wiper position.

What is the maximum clock frequency supported by the DS1267S-100/T&R serial interface?

The DS1267S-100/T&R supports a maximum CLK frequency of 10 MHz, with minimum pulse width of 50 ns for both high and low states. Timing parameters including setup (30 ns), hold (10 ns), and propagation delays (50 ns) are fully characterized across -40°C to +85°C. Exceeding 10 MHz may result in incomplete shift register loading or metastability in the RST-synchronized control logic.