My Inquiry
My Account
Analog Devices Inc./Maxim Integrated DS1345YP-100+
- Part No.:
- DS1345YP-100+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Memory
- Package:
- 34-PowerCap™ Module
- Datasheet:
-
DS1345YP-100+.pdf
- Description:
- IC NVSRAM 1MBIT PAR 34PWRCAP
- Quantity:
- Payment:
- Shipping:
Inventory:2,336
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1345YP-100+ from Maxim Integrated is a 1024kbit (131,072 × 8) nonvolatile SRAM with integrated lithium battery backup, power-fail detection, automatic write protection, and battery voltage monitoring. It operates across ±10% VCC (4.5V–5.5V), delivers 70ns read/write access time, and guarantees ≥10 years data retention without external power. It replaces 128k × 8 SRAM/EEPROM/Flash in mission-critical industrial control and metering systems.
For engineers reviewing the DS1345YP-100+ datasheet, DS1345YP-100+ pinout, DS1345YP-100+ application, or DS1345YP-100+ equivalent, key selection criteria include its PowerCap module packaging, open-drain RST/BW outputs, VTP = 4.25V write-protection threshold, 50µA typical standby current, and compatibility with DS9034PC+ PowerCap for field-replaceable battery maintenance.
Technical Context
The DS1345YP-100+ integrates static RAM, power-monitoring logic, battery-switching circuitry, and periodic battery self-test into a single 34-pin PowerCap Module. Its VCC monitor triggers RST assertion within 15µs of undervoltage detection and holds reset for 200ms during power-up to suppress transients.
Battery health is verified daily via 1-second loading with a 1MΩ resistor; if voltage drops below 2.6V, BW asserts and remains active until replacement. The device uses open-drain RST and BW outputs requiring external pull-ups and sinks up to 10mA per pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1024kbit (131,072 × 8) - supports full byte-wide data bus interfacing without address multiplexing |
| Access Time | 70ns - enables direct replacement of standard 70ns SRAMs in legacy 5V microcontroller systems |
| VCC Operating Range | 4.5V to 5.5V (±10%) - accommodates wide-tolerance 5V rails common in industrial power supplies |
| Write Protection Threshold | VTP = 4.25V (min) - initiates automatic data lockout before system brownout disrupts CPU operation |
| Standby Current | 50µA typical - minimizes battery drain during extended backup-only operation |
| Data Retention | ≥10 years without power - assured by factory-sealed lithium cell and internal disconnect switch |
| Temperature Range | -40°C to +85°C (IND grade) - qualified for uncontrolled industrial environments |
Pinout & Package
DS1345YP-100+ is housed in a 34-pin PowerCap Module (PCM) package - a surface-mountable hybrid assembly requiring separate attachment of DS9034PC+ PowerCap for full functionality. The PCM provides standardized pinout compatibility across Maxim's NV SRAM family and enables reflow soldering prior to battery installation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A16 | Address Inputs | 17-bit address bus supporting full 131,072-word addressing; no multiplexing required |
| DQ0–DQ7 | Data I/O | 8-bit bidirectional data bus compatible with standard SRAM timing and bus drivers |
| CE | Chip Enable | Active-low chip select; controls device enable and participates in write-cycle timing with WE |
| WE | Write Enable | Active-low write strobe; falling edge (with CE) initiates write; open-drain not applicable |
| OE | Output Enable | Active-low output control; disables DQ drivers during reads to prevent bus contention |
| RST | Reset Output | Open-drain power-fail warning signal; requires external pull-up; sinks 10mA |
| BW | Battery Warning | Open-drain low-battery indicator; latched active until PowerCap replacement |
| VCC | Power Supply | +5V supply input; powers logic and RAM; triggers battery switchover below ~2.7V |
| GND | Ground | Reference return path for all signals and internal switching circuitry |
| NC | No Connect | Unbonded pins (pins 17 and 34); must remain unconnected on PCB |
Key Features
| Feature | Design Value |
|---|---|
| Lithium battery disconnect at first power-up | Preserves shelf life by electrically isolating battery until initial VCC application |
| Daily battery voltage self-test | Automated 1-second 1MΩ load test every 24 hours; detects capacity degradation before failure |
| Power-fail reset generation | RST asserted within 15µs of VCC drop below VTP; held active 200ms after power restoration |
| Standardized PCM pinout | Enables drop-in replacement across Maxim's NV SRAM portfolio without layout change |
| Unlimited write endurance | Eliminates wear-out concerns in high-frequency logging or configuration storage applications |
Applications
| Smart Electricity Metering | Industrial PLC Data Logging |
|---|---|
Use Scenario: Continuous energy consumption recording with tamper-proof retention during grid outages. IC Role / Device Role / Timing Role: Nonvolatile SRAM storing meter registers, tariff tables, and event logs; RST synchronizes MCU shutdown on brownout. Use Value: Guarantees 10-year data integrity without supercapacitors or external battery management circuitry. | Use Scenario: Real-time process variable buffering in programmable logic controllers during AC power interruption. IC Role / Device Role / Timing Role: Backup memory holding ladder logic state, I/O snapshots, and alarm history; BW alerts maintenance when battery nears EOL. Use Value: Eliminates need for external EEPROM write cycles and associated firmware overhead during power transitions. |
| Medical Infusion Pump Memory | Telecom Base Station Configuration Storage |
Use Scenario: Storing calibrated dosing parameters, usage history, and safety-critical fault records. IC Role / Device Role / Timing Role: Fail-safe memory preserving therapy settings during battery swap or main power loss; VTP = 4.25V ensures early write-lock before MCU resets. Use Value: Meets IEC 62304 Class C software requirements for persistent data retention without external supervision. | Use Scenario: Holding baseband processor configuration, calibration coefficients, and boot parameters across repeated power cycles. IC Role / Device Role / Timing Role: High-reliability SRAM replacement for Flash in control-plane subsystems; RST coordinates graceful firmware save before shutdown. Use Value: Avoids Flash write latency and erase-cycle limitations in time-sensitive telecom control paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar nonvolatile SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1345ABP-70IND+ | VCC tolerance ±5% (4.75–5.25V); higher VTP = 4.5V; identical pinout and PCM package | Better suited for tightly regulated 5V systems where earlier write-protection is acceptable | Select DS1345ABP-70IND+ when system VCC ripple is <±2.5% and deterministic brownout response is prioritized over wide-rail flexibility |
| STK13C68-J15F | 1024kbit NV SRAM; 15ns access; 3.3V only; SOIC-32 package; no integrated battery monitor or BW output | Lacks daily battery test and open-drain BW; requires external supervisor for reset coordination | Choose STK13C68-J15F only for cost-sensitive 3.3V designs where battery health monitoring is handled externally |
Compared with DS1345ABP-70IND+, DS1345YP-100+ offers wider VCC tolerance and lower VTP for earlier fail-safe locking, while STK13C68-J15F trades integrated monitoring for faster access and lower voltage operation but demands additional support components.
Availability
DS1345YP-100+ is available at Aetrix Electronics and suitable for smart metering, industrial PLC data logging, medical infusion pump memory, and telecom base station configuration storage requiring stable component supply, long-term lifecycle assurance, and field-replaceable battery capability.
Supply support for DS1345YP-100+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for industrial, automotive, and communications applications.
The DS1345Y product line delivers integrated nonvolatile SRAM modules with autonomous power monitoring and battery management - engineered specifically for systems demanding zero-data-loss memory retention during unpredictable power interruptions.
FAQ
What is the guaranteed data retention period for DS1345YP-100+?
The DS1345YP-100+ guarantees ≥10 years of data retention in the absence of external power, measured from the time VCC is first applied. This is achieved through a factory-sealed lithium cell, internal disconnect switch, and controlled discharge path - all validated per Maxim's component selection and process control protocols. The DS1345YP-100+ does not require external capacitors or refresh circuitry to meet this specification.
Does DS1345YP-100+ require an external PowerCap, and which one?
Yes, DS1345YP-100+ requires a separate DS9034PC+ or DS9034PCI+ PowerCap to be snapped onto the 34-pin PCM substrate after reflow soldering. The DS9034PC+ provides the lithium backup battery and mates mechanically via keyed alignment. DS1345YP-100+ cannot function as a nonvolatile memory without this attached PowerCap, as the battery is electrically disconnected until first VCC application.
How does the battery warning (BW) output behave on DS1345YP-100+?
The BW output on DS1345YP-100+ is an open-drain signal that asserts low when battery voltage falls below 2.6V during its daily 1-second 1MΩ test. Once activated, BW remains latched low until the DS9034PC+ PowerCap is physically replaced. Even after replacement, BW de-asserts only after the next successful battery test confirms voltage >2.6V - ensuring reliable end-of-life detection without false positives.
What is the function of the RST pin on DS1345YP-100+?
The RST pin on DS1345YP-100+ is an open-drain reset output that warns the host processor of impending power failure by asserting low when VCC drops below VTP (4.25V min). It remains active for 200ms after VCC rises above VTP during power-up to suppress startup transients. External pull-up is mandatory, and RST sinks up to 10mA - enabling direct connection to most microcontroller reset inputs without level-shifting.
Can DS1345YP-100+ operate in a 3.3V system?
No, DS1345YP-100+ is specified only for 5V operation with ±10% tolerance (4.5V–5.5V). Its internal voltage monitors, write-protection threshold (VTP = 4.25V), and logic thresholds are designed exclusively for 5V-compatible interfaces. Attempting to power DS1345YP-100+ from 3.3V will result in failure to initialize, incorrect RST/BW behavior, and unreliable memory access - it is not interoperable with 3.3V systems without level translation and external regulation.
DS1345YP-100+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 34-PowerCap™ Module
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- NVSRAM
- Technology:
- NVSRAM (Non-Volatile SRAM)
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 100ns
- Access Time:
- 100 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 34-PowerCap Module
DS1345YP-100+ FAQ
1.How can I place an order for DS1345YP-100+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1345YP-100+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1345YP-100+ reliable?
The price and inventory of DS1345YP-100+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1345YP-100+ is usually 5 days.
3.What payment methods are accepted for DS1345YP-100+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1345YP-100+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1345YP-100+?
DS1345YP-100+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1345YP-100+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1345YP-100+?
For technical support, including DS1345YP-100+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1345YP-100+ requirements.
6.How does Aetrix verify that DS1345YP-100+ is sourced from the original manufacturer or authorized distributors?
All DS1345YP-100+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1345YP-100+ meets industry standards.
7.What is the process for return or replacement of DS1345YP-100+?
All DS1345YP-100+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1345YP-100+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1345YP-100+ part is unused and in its original packaging.
Return procedure for DS1345YP-100+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1345YP-100+ Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
