Analog Devices Inc./Maxim Integrated DS1706LEPA+

Overview

DS1706LEPA+ from Maxim Integrated is a 5V ±5% microprocessor supervisory circuit that provides power-on reset, watchdog timer, and non-maskable interrupt functions in an 8-pin PDIP package. It monitors VCC for out-of-tolerance conditions, generates a 130 ms minimum active-high RST output, debounces pushbutton resets, and delivers a 1-second watchdog timeout with WDS status output - all within -40°C to +85°C industrial temperature range.

For engineers reviewing the DS1706LEPA+ datasheet, DS1706LEPA+ pinout, DS1706LEPA+ application, or DS1706LEPA+ equivalent, key selection considerations include its active-high reset output (RST), 4.65 V typical VCC trip point, 130 ms reset pulse width, watchdog timeout accuracy, and compatibility with 5V microprocessor systems requiring early power-fail warning via NMI.

Technical Context

The DS1706LEPA+ integrates three independent monitoring functions: precision VCC threshold detection using an internal bandgap reference (1.25 V IN trip point), pushbutton reset debouncing with guaranteed 130 ms active-high reset assertion, and a 1-second watchdog timer triggered by ST strobe input transitions. Its NMI output pulses low for ≥200 µs upon voltage decay at the IN pin, providing early warning before RST activation.

It operates across 1.2 V to 5.5 V supply range with 50 µA typical ICC at VCC < 3.6 V, supports external voltage sensing via resistor divider on IN, and features built-in hysteresis (100 µV) and noise immunity (<2 µs pulses ignored) to prevent false interrupts during power transients.

Key Specifications

Pinout & Package

DS1706LEPA+ is housed in an 8-pin plastic DIP (300-mil) package with through-hole mounting and industry-standard footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX706ESA+, DS1706LEPA+ provides native active-high reset without external inversion; compared with TPS3808G15DBVR, it adds critical NMI and watchdog capabilities essential for safety-critical or unattended embedded systems.

Availability

DS1706LEPA+ is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, telecom infrastructure, and automotive electronics requiring stable component supply and long-term lifecycle support.

Supply support for DS1706LEPA+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in analog, mixed-signal, and power management ICs for industrial, communications, and computing applications.

The DS1706LEPA+ belongs to the MicroMonitor™ family of supervisory circuits designed specifically for robust microprocessor reset, watchdog, and power-fail warning in mission-critical embedded systems operating across extended temperature ranges.

FAQ

What is the reset output polarity of DS1706LEPA+?

The DS1706LEPA+ features an active-high reset output (RST), distinct from variants like DS1706EPA+ which provide active-low /RST. This eliminates the need for external inverters in systems requiring high-true reset assertion, simplifying PCB design and reducing component count. The RST signal remains asserted for a guaranteed minimum of 130 ms during power-up or brownout recovery, ensuring reliable microprocessor initialization.

Does DS1706LEPA+ support external voltage monitoring beyond VCC?

Yes, DS1706LEPA+ supports external voltage monitoring via its IN pin, which has a precise 1.25 V ±0.05 V internal reference threshold. By connecting a resistor divider between the target supply rail and ground, users can monitor higher voltages (e.g., 12 V, 24 V) or secondary regulated rails. The IN pin's high impedance (>100 MΩ) ensures minimal loading, and its hysteresis (100 µV) prevents false triggers from noise - making DS1706LEPA+ suitable for upstream power rail supervision in complex power architectures.

What is the watchdog timeout behavior of DS1706LEPA+?

The DS1706LEPA+ watchdog timer times out after 1.0–2.2 seconds if the ST input does not receive a high-to-low transition. Upon timeout, the WDS output goes active-low for ≥130 ms, signaling a software hang. The timer starts counting only after RST becomes inactive, ensuring it does not trigger during power-up. ST can be driven by any microprocessor signal (e.g., address, data, or control lines) that toggles regularly - giving designers flexibility to implement fail-safe supervision without dedicated timer peripherals.

How does DS1706LEPA+ handle pushbutton reset inputs?

DS1706LEPA+ debounces the PBRST input internally and guarantees a minimum 130 ms RST pulse width upon button release. The PBRST pin is internally pulled up to VCC (40 kΩ typical), requiring only a simple switch-to-ground connection. No external RC network is needed. Additionally, PBRST can be driven by other outputs - such as NMI or WDS - enabling automatic reset generation after early warning or watchdog timeout, enhancing system autonomy without firmware intervention.

Is DS1706LEPA+ compatible with the MAX705/MAX706 family?

Yes, DS1706LEPA+ is pin-compatible with the MAX705/MAX706 in 8-pin DIP, SOIC, and µSOP packages, sharing identical pin assignments and functional mapping. However, DS1706LEPA+ differs in its reset polarity (RST vs. /RST) and specific VCC trip point (4.65 V typical for ±5% 5V monitoring). Designers migrating from MAX706 should verify reset logic polarity and confirm compatibility with existing firmware or downstream reset conditioning circuits.