My Inquiry
My Account
Analog Devices Inc./Maxim Integrated DS1706PESA+T&R
- Part No.:
- DS1706PESA+T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1706PESA+T&R.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,412
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1706PESA+T&R from Maxim Integrated is a 3.3V ±20% precision microprocessor supervisory circuit with active-high reset output (RST), watchdog timer, non-maskable interrupt (NMI), and pushbutton reset control in an 8-pin SOIC package. It monitors VCC, detects power transients, provides early warning via NMI, and guarantees 130 ms minimum reset pulse width for reliable microprocessor recovery in industrial embedded systems.
For engineers reviewing the DS1706PESA+T&R datasheet, DS1706PESA+T&R pinout, DS1706PESA+T&R application, or DS1706PESA+T&R equivalent, key selection criteria include its 3.3V supply monitoring tolerance, RST output polarity, watchdog timeout of 1.0–2.2 s, -40°C to +85°C operation, and pin compatibility with MAX705/MAX706 in SOIC-8.
Technical Context
The DS1706PESA+T&R implements three independent monitoring functions: (1) VCC supervision with 2.55–2.70 V trip point and 130–285 ms reset assertion time; (2) pushbutton reset debouncing with guaranteed 130 ms active-high RST pulse; (3) watchdog timer with 1.0–2.2 s timeout triggered by ST input strobes and indicated by WDS low pulse.
Its IN pin accepts external voltage sense points via resistor divider (VTP = 1.25 V ±50 mV), enabling upstream power rail monitoring; NMI asserts for ≥200 µs upon undervoltage detection with 100 µV hysteresis and 5 µs noise immunity; RST remains active for ≥130 ms after VCC recovery to ensure processor stabilization.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Trip Point | 2.55–2.70 V - precisely targets 3.3V systems operating at reduced margin (e.g., 3.0V nominal rails) |
| Reset Output Polarity | Active-high RST - directly drives reset inputs requiring high-level assertion without external inversion |
| Watchdog Timeout | 1.0–2.2 s - configurable timing window for software execution verification before system lockup |
| Reset Pulse Width | ≥130 ms - ensures sufficient duration for microprocessor power-up sequencing and clock stabilization |
| Operating Temperature | -40°C to +85°C - supports deployment in industrial control, automation, and harsh-environment embedded systems |
| Supply Current | 50 µA @ VCC < 3.6V - enables low-power operation in battery-backed or energy-constrained applications |
| NMI Response Time | 5–8 µs - delivers fast early-warning interrupt before VCC collapse reaches critical threshold |
Pinout & Package
DS1706PESA+T&R is housed in an 8-pin SOIC (150-mil) surface-mount package compliant with JEDEC MS-012, with 1.27 mm pitch and standard land pattern S8-2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PBRST | Pushbutton Reset Input | Active-low debounced input; initiates ≥130 ms RST pulse on release, supporting manual system recovery |
| VCC | Power Supply | Primary 3.3V supply input; monitored for undervoltage with 2.55–2.70 V trip threshold |
| GND | Ground Reference | System ground return path for all internal comparators, timers, and outputs |
| IN | Voltage Sense Input | High-impedance (≤1 µA leakage) input for external resistor-divider monitoring of upstream rails (VTP = 1.25 V) |
| NMI | Non-Maskable Interrupt Output | Open-drain active-low output; pulses ≥200 µs to warn CPU of impending power failure |
| ST | Strobe Input | Watchdog trigger input; requires high-to-low transition every ≤1.0 s to prevent WDS activation |
| RST | Active-High Reset Output | Push-pull output asserting high for ≥130 ms during power-up, brownout, or PBRST event |
| WDS | Watchdog Status Output | Open-drain active-low output pulsed ≥130 ms if ST is not strobed within watchdog timeout |
Key Features
| Feature | Design Value |
|---|---|
| 3.3V ±20% VCC Monitoring | Enables robust supervision of 3.0V nominal systems where supply tolerance is relaxed, eliminating need for external resistive dividers |
| Active-High RST Output | Directly interfaces with microprocessors requiring high-level reset assertion (e.g., ARM Cortex-M, Renesas RX), avoiding level-shifting components |
| Integrated Watchdog Timer | Self-contained 1.0–2.2 s timeout eliminates discrete RC timing networks and reduces BOM count in safety-critical firmware recovery paths |
| Non-Maskable Interrupt (NMI) | Provides deterministic early-warning signal (≥200 µs pulse) for controlled shutdown or state save before full reset, improving system data integrity |
| Pushbutton Reset Debouncing | On-chip RC filtering and timing guarantee clean 130 ms RST pulse regardless of mechanical switch bounce, simplifying front-panel design |
Applications
| Industrial PLC Controller | Medical Diagnostic Equipment |
|---|---|
Use Scenario: Power supply monitoring and firmware watchdog in programmable logic controllers deployed in factory automation environments with variable line voltage and EMI exposure. IC Role / Device Role / Timing Role: Supervisory IC providing VCC brownout detection, NMI-triggered graceful I/O shutdown, and RST-driven cold restart after power interruption. Use Value: Prevents corrupted ladder logic execution and ensures deterministic recovery from transient grid sags, meeting IEC 61000-4-11 immunity requirements. | Use Scenario: Critical power management in portable ultrasound or patient monitor units where battery voltage decay must trigger orderly data save before shutdown. IC Role / Device Role / Timing Role: Dual-role supervisor: IN pin monitors battery-derived 3.3V rail; WDS output signals firmware to initiate flash write and suspend display updates. Use Value: Guarantees ≥130 ms reset hold time for NAND flash programming completion and preserves last vital vitals snapshot during power loss. |
| Telecom Remote Terminal Unit | Smart Energy Meter |
Use Scenario: Embedded communication module in outdoor RTUs exposed to wide temperature swings (-40°C to +85°C) and lightning-induced surges on DC power lines. IC Role / Device Role / Timing Role: Primary power supervisor detecting upstream 3.3V rail collapse; NMI alerts host MCU to flush serial buffers before RST assertion. Use Value: Maintains UART packet integrity during AC/DC converter faults by decoupling early warning (NMI) from hard reset (RST), reducing frame loss. | Use Scenario: Tamper-resistant metering platform requiring secure boot and runtime integrity checks under fluctuating utility-supplied DC rails. IC Role / Device Role / Timing Role: Watchdog supervisor verifying firmware heartbeat via ST input tied to timer interrupt; RST forces secure reinitialization if crypto engine hangs. Use Value: Enforces mandatory 1.0–2.2 s software liveness check interval, satisfying ANSI C12.22 security compliance for firmware update rollback prevention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX706TESA+ | 3.3V ±5% trip point (3.135–3.315 V); active-low /RST output; no RST pin | Suitable for tighter-tolerance 3.3V rails where precise threshold is required; lacks active-high reset option | Select when system reset logic expects low-active assertion and higher accuracy is prioritized over flexibility in reset polarity |
| TPS3808G33DBVR | 3.3V ±2% trip point; fixed 200 ms reset delay; no NMI or watchdog strobe input | Optimized for simple power-on reset only; missing early-warning interrupt and software watchdog features | Choose for cost-sensitive applications needing basic POR without advanced supervision or firmware interaction |
Compared with MAX706TESA+ and TPS3808G33DBVR, DS1706PESA+T&R uniquely combines 3.3V ±20% tolerance, active-high RST, integrated NMI, and user-controllable watchdog-making it optimal for industrial systems requiring both fault prediction and deterministic recovery.
Availability
DS1706PESA+T&R is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, telecom infrastructure, and smart metering applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for DS1706PESA+T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for industrial, automotive, communications, and computing markets.
The DS1706PESA+T&R belongs to the MicroMonitor family-engineered specifically for microprocessor reliability in harsh environments, integrating power monitoring, watchdog, and reset control in single-chip solutions.
FAQ
What is the exact VCC trip point range for DS1706PESA+T&R?
The DS1706PESA+T&R has a guaranteed VCC trip point range of 2.55 V to 2.70 V, corresponding to its 3.3V ±20% specification. This range is validated across the full -40°C to +85°C operating temperature and ensures reliable detection of brownout conditions in 3.0V nominal systems. The DS1706PESA+T&R datasheet specifies VCCTP = 2.55/2.63/2.70 V (min/typ/max) under recommended operating conditions.
Does DS1706PESA+T&R provide both active-high and active-low reset outputs?
No, DS1706PESA+T&R provides only an active-high RST output. The "P" suffix in the part number explicitly denotes the RST (not /RST) variant. Unlike DS1706RESA+T&R which offers active-low /RST, the DS1706PESA+T&R uses push-pull RST to assert high during reset events. Its pinout includes RST but omits /RST, confirming single-polarity reset capability.
How does the watchdog timer in DS1706PESA+T&R interact with the reset function?
The DS1706PESA+T&R watchdog timer operates independently of the VCC monitor: it starts timing after RST becomes inactive and triggers WDS low if ST is not strobed within 1.0–2.2 s. WDS does not directly assert RST; instead, it signals firmware to take corrective action. However, connecting WDS to PBRST (as shown in Figure 3 of the datasheet) enables automatic RST assertion on timeout-making DS1706PESA+T&R capable of full hardware-initiated recovery.
Can DS1706PESA+T&R monitor voltages other than its own VCC supply?
Yes, DS1706PESA+T&R can monitor external voltage rails using its IN pin. With a precision 1.25 V ±50 mV internal reference, the IN pin accepts divided-down voltages from higher rails (e.g., 12V, 5V) via an external resistor network. The DS1706PESA+T&R datasheet provides the formula VSENSE = (R2/(R1+R2)) × 1.25 V and confirms IN is high-impedance (leakage ≤±1 µA), enabling flexible upstream power rail supervision without loading sensitive sources.
Is DS1706PESA+T&R pin-compatible with legacy Maxim supervisory ICs?
Yes, DS1706PESA+T&R is pin-compatible with the MAX705/MAX706 in 8-pin SOIC (S8-2) packaging, sharing identical pin assignments for VCC, GND, IN, NMI, ST, RST, PBRST, and WDS. This allows drop-in replacement in existing designs using those Maxim parts, provided the reset polarity (RST vs /RST) and trip point (3.3V ±20%) match system requirements. The DS1706PESA+T&R datasheet explicitly states this compatibility in the Features section.
DS1706PESA+T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- MicroMonitor™
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 2.63V
- Output:
- Push-Pull, Totem Pole
- Reset:
- Active High
- Reset Timeout:
- 130ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1706PESA+T&R FAQ
1.How can I place an order for DS1706PESA+T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1706PESA+T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1706PESA+T&R reliable?
The price and inventory of DS1706PESA+T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1706PESA+T&R is usually 5 days.
3.What payment methods are accepted for DS1706PESA+T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1706PESA+T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1706PESA+T&R?
DS1706PESA+T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1706PESA+T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1706PESA+T&R?
For technical support, including DS1706PESA+T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1706PESA+T&R requirements.
6.How does Aetrix verify that DS1706PESA+T&R is sourced from the original manufacturer or authorized distributors?
All DS1706PESA+T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1706PESA+T&R meets industry standards.
7.What is the process for return or replacement of DS1706PESA+T&R?
All DS1706PESA+T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1706PESA+T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1706PESA+T&R part is unused and in its original packaging.
Return procedure for DS1706PESA+T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1706PESA+T&R Tags
-
MIC826SYMT-TR
Microchip Technology
-
APX803S-31SA-7
Diodes Incorporated
-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments
-
V6340RSP3B+
EM Microelectronic
-
EM6325CXSP5B-2.9+
EM Microelectronic
-
MCP120T-300I/TT
Microchip Technology
-
MCP130T-315I/TT
Microchip Technology
-
MCP120T-475I/TT
Microchip Technology
-
MCP111T-300E/TT
Microchip Technology
-
MCP120T-315I/TT
Microchip Technology
-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
