Analog Devices Inc./Maxim Integrated DS1706SEUA/T&R
- Part No.:
- DS1706SEUA/T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
DS1706SEUA/T&R.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 8UMAX
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1706SEUA/T&R from Maxim Integrated is a 3.3V ±10% supply voltage supervisor IC with active-low reset output (/RST), watchdog timer, non-maskable interrupt (NMI), and pushbutton reset debouncing - designed for microprocessor monitoring in embedded systems requiring reliable power-up/power-down sequencing and fault recovery. It delivers 130 ms minimum reset pulse width, 1 s watchdog timeout, and operates across -40°C to +85°C.
For engineers reviewing the DS1706SEUA/T&R datasheet, DS1706SEUA/T&R pinout, DS1706SEUA/T&R application, or DS1706SEUA/T&R equivalent, key selection criteria include VCC trip point accuracy (2.85–3.00 V), /RST assertion timing (130–285 ms), industrial temperature range, µSOP-8 package compatibility, and functional alignment with 3.3V microcontroller power management requirements.
Technical Context
The DS1706SEUA/T&R implements three independent monitoring functions: precision VCC supervision using an internal bandgap reference and comparator (trip point 2.85–3.00 V), a 1-second watchdog timer triggered by ST input strobes, and a debounced pushbutton reset input (PBRST) that guarantees ≥130 ms /RST pulse on release. All functions operate within a single 8-pin µSOP package.
It provides dual reset signaling: active-low /RST output and NMI output for early power-fail warning (200 µs pulse at IN trip point of 1.25 V), with built-in hysteresis (100 µV) and noise immunity (<2 µs glitches rejected). The IN pin supports external voltage sensing via resistor divider, enabling upstream supply monitoring before VCC collapse.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Trip Point | 2.85–3.00 V (±10% tolerance for 3.3V systems; ensures reset activation before microprocessor brownout) |
| Reset Pulse Width | 130–285 ms (guaranteed minimum 130 ms /RST assertion during power-up or fault, allowing full system stabilization) |
| Watchdog Timeout | 1.0–2.2 s (configurable via ST strobe frequency; forces WDS low if microprocessor fails to refresh within interval) |
| NMI Pulse Width | ≥200 µs (early warning signal generated when monitored supply decays to 1.25 V sense threshold) |
| Operating Temperature | -40°C to +85°C (industrial-grade thermal range suitable for harsh embedded environments) |
| Supply Current | 50 µA (at VCC < 3.6 V; enables ultra-low-power operation in battery-backed or energy-constrained systems) |
| Package | 8-pin µSOP (118-mil width; surface-mount footprint compatible with high-density PCB layouts) |
Pinout & Package
DS1706SEUA/T&R is housed in an 8-pin µSOP (118-mil) package, pin-compatible with DS1706 variants in DIP and SOIC packages. Pin assignments are standardized across the DS1705/DS1706 family.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PBRST | Pushbutton Reset Input | Active-low, internally pulled up (40 kΩ typical); debounced to generate ≥130 ms /RST pulse on button release |
| VCC | Power Supply Input | Primary supply rail (1.2–5.5 V); powers all internal circuits and sets trip point reference |
| GND | Ground Reference | System ground return path for all analog and digital functions |
| IN | External Voltage Sense Input | High-impedance (≤1 µA leakage) input referenced to 1.25 V internal bandgap; used with resistor divider to monitor upstream supplies |
| NMI | Non-Maskable Interrupt Output | Open-drain, active-low output pulsed ≥200 µs when IN falls below 1.25 V; enables early software shutdown |
| ST | Watchdog Strobe Input | Active-high input (internally pulled up 180 kΩ); must be toggled low at least once per 1 s to prevent WDS activation |
| /RST | Active-Low Reset Output | Open-drain output asserted low during VCC fault, power-up, or PBRST event; held ≥130 ms minimum |
| WDS | Watchdog Status Output | Open-drain, active-low output driven low for ≥130 ms upon watchdog timeout; can feed back to PBRST for auto-recovery |
Key Features
| Feature | Design Value |
|---|---|
| Triple-function supervision | Integrates VCC monitoring, pushbutton reset control, and watchdog timer in one 8-pin µSOP - eliminates discrete RC networks and logic gates |
| Configurable reset threshold | 2.85–3.00 V trip point (±10% for 3.3V systems) ensures compatibility with modern low-voltage microcontrollers without external scaling |
| Early-warning NMI output | Generates ≥200 µs interrupt at 1.25 V sense point with 100 µV hysteresis - provides deterministic time margin for controlled firmware shutdown before /RST asserts |
| Robust pushbutton interface | Hardware debouncing and guaranteed 130 ms /RST pulse eliminate need for external timers or microcontroller GPIO polling |
| Watchdog feedback capability | WDS output can drive PBRST to trigger automatic system reset after timeout - enables self-healing behavior without host intervention |
Applications
| Industrial PLC Controller | Medical Diagnostic Device |
|---|---|
|
Use Scenario: Microcontroller-based programmable logic controller operating in factory-floor environments with fluctuating 3.3V supply rails and EMI exposure. IC Role / Device Role / Timing Role: Primary VCC supervisor and watchdog enforcer; monitors 3.3V rail, asserts /RST on brownout, and triggers NMI for graceful I/O state freeze prior to reset. Use Value: Prevents corrupted ladder logic execution during voltage transients; 130 ms reset hold ensures FPGA configuration completes before MCU boot. |
Use Scenario: Portable ultrasound imaging unit powered by Li-ion battery with regulated 3.3V domain feeding ADC, DSP, and display controller. IC Role / Device Role / Timing Role: Power integrity guardian; senses upstream DC-DC output via IN pin, generates NMI for data buffer flush, then /RST to restart acquisition chain after undervoltage. Use Value: Guarantees zero image frame loss during battery sag; 2.85 V trip point aligns precisely with 3.3V LDO dropout margin. |
| Automotive Infotainment Head Unit | Smart Energy Meter |
|
Use Scenario: ARM Cortex-A based infotainment system exposed to automotive load-dump and cold-crank transients on 3.3V core rail. IC Role / Device Role / Timing Role: Fault detector and recovery initiator; uses ST input tied to UART TX line to detect firmware hang, forcing WDS→PBRST auto-reset loop. Use Value: Eliminates need for manual power cycle; 1 s watchdog timeout matches typical UI task scheduler period, catching unresponsive GUI threads. |
Use Scenario: ANSI C12.22-compliant electricity meter with isolated 3.3V microcontroller domain powered from AC-DC converter with variable line conditions. IC Role / Device Role / Timing Role: Dual-supply monitor; IN pin senses raw 12V bus via resistor divider, while VCC monitors regulated 3.3V - enables tiered response (NMI → log → /RST). Use Value: Meets IEC 62053-21 tamper detection latency requirements; 100 µV hysteresis prevents false NMI from switching noise on 12V rail. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervision applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX706TESA | Same 3.3V ±5% trip point (2.93–3.08 V), identical µSOP-8 package, but lacks NMI output and IN sense pin - only monitors VCC directly. | No early-warning capability; cannot monitor upstream supplies or implement tiered shutdown sequences. | Select when only basic VCC reset is required and board space allows omission of NMI routing. |
| TPS3808G12DBVR | 3.3V ±1.5% trip point (3.25–3.35 V), adjustable reset delay (0–10 s), no watchdog or NMI - offers tighter tolerance but fewer supervision modes. | Higher accuracy but no fault escalation path; requires external circuitry for pushbutton debounce or watchdog emulation. | Prefer for precision power-rail monitoring where deterministic reset timing outweighs multi-function integration. |
Compared with MAX706TESA and TPS3808G12DBVR, DS1706SEUA/T&R uniquely combines ±10% 3.3V supervision, hardware-debounced pushbutton support, NMI-based early warning, and integrated watchdog - delivering complete fault coverage in a single µSOP-8 footprint without external components.
Availability
DS1706SEUA/T&R is available at Aetrix Electronics and suitable for industrial automation controllers, portable medical instruments, automotive infotainment units, and smart utility meters requiring stable component supply and long-term lifecycle support.
Supply support for DS1706SEUA/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for industrial, automotive, and communications applications.
The DS1706SEUA/T&R belongs to the MicroMonitor™ family - engineered specifically for robust microprocessor supervision in mission-critical embedded systems where power integrity, fault detection speed, and autonomous recovery are essential.
FAQ
What is the exact VCC trip point range for DS1706SEUA/T&R?
The DS1706SEUA/T&R has a guaranteed VCC trip point range of 2.85 V to 3.00 V, corresponding to ±10% tolerance for nominal 3.3V systems. This specification is validated across the full -40°C to +85°C operating temperature range and is defined in the device's DC Electrical Characteristics table. The DS1706SEUA/T&R uses an internal temperature-compensated bandgap reference to maintain this accuracy without external calibration.
Does DS1706SEUA/T&R provide both active-high and active-low reset outputs?
No, DS1706SEUA/T&R provides only an active-low reset output (/RST). The datasheet confirms that DS1706SEUA/T&R is configured for /RST and /WDS outputs - unlike DS1706LEUA (which provides RST) or DS1706PEUA (which provides RST). The /RST pin is open-drain and requires an external pull-up resistor to VCC or another logic rail.
Can DS1706SEUA/T&R monitor a voltage higher than its VCC supply?
Yes, DS1706SEUA/T&R can monitor voltages higher than VCC using the IN pin with an external resistor divider. The IN pin has a fixed 1.25 V internal trip threshold and high input impedance (≤1 µA leakage), allowing safe scaling of inputs up to VCC (e.g., 12V sensed via R1/R2 network). The DS1706SEUA/T&R datasheet provides the exact formula for calculating R1 and R2 values based on desired sense voltage.
What is the watchdog timeout behavior of DS1706SEUA/T&R?
The DS1706SEUA/T&R watchdog timer times out after 1.0–2.2 seconds if the ST input is not strobed low before expiration. Upon timeout, the WDS output is driven active-low for ≥130 ms. The watchdog starts counting only after /RST becomes inactive (i.e., after power-up stabilization), and each ST low pulse resets the timer. This behavior is fully specified in the AC Electrical Characteristics table under parameter tTD.
Is DS1706SEUA/T&R pin-compatible with other DS1706 variants?
Yes, DS1706SEUA/T&R is pin-compatible with all DS1706 family members in the same package type - including DS1706TEUA, DS1706PEUA, and DS1706REUA - all use the identical 8-pin µSOP (118-mil) footprint and pinout. This allows direct substitution within the same package variant, though trip point, reset polarity, and feature set (e.g., NMI presence) differ between suffixes.
DS1706SEUA/T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- MicroMonitor™
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 2.93V
- Output:
- Push-Pull, Totem Pole
- Reset:
- Active Low
- Reset Timeout:
- 130ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-uMAX/uSOP
DS1706SEUA/T&R FAQ
1.How can I place an order for DS1706SEUA/T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1706SEUA/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1706SEUA/T&R reliable?
The price and inventory of DS1706SEUA/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1706SEUA/T&R is usually 5 days.
3.What payment methods are accepted for DS1706SEUA/T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1706SEUA/T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1706SEUA/T&R?
DS1706SEUA/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1706SEUA/T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1706SEUA/T&R?
For technical support, including DS1706SEUA/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1706SEUA/T&R requirements.
6.How does Aetrix verify that DS1706SEUA/T&R is sourced from the original manufacturer or authorized distributors?
All DS1706SEUA/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1706SEUA/T&R meets industry standards.
7.What is the process for return or replacement of DS1706SEUA/T&R?
All DS1706SEUA/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1706SEUA/T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1706SEUA/T&R part is unused and in its original packaging.
Return procedure for DS1706SEUA/T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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