Analog Devices Inc./Maxim Integrated DS1708TESA+

Overview

DS1708TESA+ from Maxim Integrated is a 3.3V ±5% precision voltage supervisor IC that monitors VCC, senses external supply voltage via high-impedance IN pin, and debounces pushbutton reset input. It delivers active-low and active-high reset outputs (RST and RST), non-maskable interrupt (NMI), and guarantees ≥130 ms reset pulse width. Used in embedded microprocessor systems requiring reliable power-up sequencing and early power-fail warning.

For engineers reviewing the DS1708TESA+ datasheet, DS1708TESA+ pinout, DS1708TESA+ application, or DS1708TESA+ equivalent, key selection criteria include its 3.3V ±5% VCC trip point (VCCTP = 3.00–3.15 V), dual reset outputs, NMI generation at 1.25 V IN threshold, industrial temperature range (−40°C to +85°C), and SOIC-8 package compatibility with legacy MAX707/MAX708 designs.

Technical Context

The DS1708TESA+ integrates three independent monitoring functions: VCC supply supervision with temperature-compensated bandgap reference, high-impedance voltage sense input (IN) for upstream power rail monitoring, and debounced pushbutton reset (PBRST) with guaranteed 130 ms output pulse. Its dual reset outputs (RST and RST) provide simultaneous active-low and active-high signaling for diverse processor interface requirements.

It generates a non-maskable interrupt (NMI) when the IN pin voltage falls below 1.20–1.30 V, with built-in 100 µV hysteresis and 5 µs noise immunity. Reset assertion persists for ≥130 ms after VCC recovery, ensuring stable processor initialization. The device draws only 50 µA typical current at VCC < 3.6 V and operates across 1.2–5.5 V supply range.

Key Specifications

Pinout & Package

DS1708TESA+ is housed in an 8-pin SOIC (150-mil) package, pin-compatible with MAX707/MAX708 and other industry-standard supervisory ICs. Pin assignments are standardized across DIP, SOIC, and µSOP variants per Maxim's mechanical drawings.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage supervisor applications.

Compared with MAX708ESA+, DS1708TESA+ adds IN-sense and NMI for proactive power management; compared with TPS3808G33DBVR, it trades tighter trip tolerance for dual reset polarity and interrupt-driven shutdown - making DS1708TESA+ optimal for systems needing both robust reset timing and early fault notification.

Availability

DS1708TESA+ is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, telecom infrastructure, and automotive infotainment systems requiring stable component supply, long-term lifecycle support, and guaranteed SOIC-8 packaging.

Supply support for DS1708TESA+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for industrial, communications, and computing applications.

The DS1707/DS1708 family was designed specifically for microprocessor supervision in systems demanding simultaneous reset assertion, early power-fail warning, and pushbutton-controlled recovery - targeting embedded controllers where reliability under voltage transients is mission-critical.

FAQ

What is the exact VCC trip point range for DS1708TESA+?

The DS1708TESA+ has a specified VCC trip point (VCCTP) of 3.00 V minimum, 3.08 V typical, and 3.15 V maximum - corresponding to a ±5% tolerance around 3.3 V nominal. This range is validated across the full −40°C to +85°C operating temperature and ensures consistent brown-out detection without external calibration. The DS1708TESA+ uses an internal temperature-compensated bandgap reference to maintain this accuracy over process and temperature variation.

Does DS1708TESA+ support monitoring of voltages higher than 3.3 V?

Yes, DS1708TESA+ supports monitoring of higher-voltage rails via its high-impedance IN pin, which triggers NMI when the voltage at that pin drops below 1.20–1.30 V. A resistor divider (e.g., R1 = 26 kΩ, R2 = 10 kΩ) scales a 4.5 V rail down to 1.25 V at IN, enabling early detection of upstream supply decay. The DS1708TESA+ datasheet provides the exact equation for calculating divider values and confirms VMAX = (VTP / VSENSE) × VCC, limiting input to safe levels.

How does the pushbutton reset function work on DS1708TESA+?

The DS1708TESA+ PBRST pin accepts an active-low signal and internally debounces it using hardware timing logic. When the button is released, DS1708TESA+ guarantees a reset pulse width of ≥130 ms on both RST and RST outputs - independent of press duration or contact bounce. This eliminates the need for external RC filters or firmware polling. The DS1708TESA+ also allows NMI to be connected to PBRST for automatic reset initiation upon power-fail detection.

What is the purpose of the dual reset outputs (RST and RST) on DS1708TESA+?

The DS1708TESA+ provides RST (active-low, open-drain) and RST (active-high, push-pull) to accommodate diverse microprocessor and FPGA reset interface requirements without external logic. RST interfaces directly with processors expecting active-low reset (e.g., many ARM cores), while RST drives high during fault conditions for devices requiring active-high assertion (e.g., certain FPGAs or ASICs). This dual-output architecture simplifies board design and avoids level translators or inverters in mixed-signaling systems.

Is DS1708TESA+ pin-compatible with MAX707/MAX708 devices?

Yes, DS1708TESA+ is explicitly documented as pin-compatible with MAX707/MAX708 in 8-pin SOIC (150-mil), DIP (300-mil), and µSOP (118-mil) packages. Pin functions match exactly: PBRST, VCC, GND, IN, RST, RST, NC, and NMI occupy identical positions across all three footprints. This allows drop-in replacement in existing designs using MAX707ESA+/MAX708ESA+, provided the 3.3 V ±5% trip point meets system requirements.