Analog Devices Inc./Maxim Integrated DS1708TESA/T&R/
- Part No.:
- DS1708TESA/T&R/
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1708TESA/T&R/.pdf
- Description:
- DS1708 5.0-VOLT MICROMONITOR
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1708TESA/T&R/ from Maxim Integrated is a 3.3V ±5% precision voltage supervisor IC with dual active-high/active-low reset outputs, non-maskable interrupt (NMI), and pushbutton reset debouncing - designed for microprocessor power monitoring in industrial embedded systems. It provides 130ms minimum reset pulse width, 1.25V internal reference for external voltage sensing, and operates across –40°C to +85°C.
For engineers reviewing the DS1708TESA/T&R/ datasheet, DS1708TESA/T&R/ pinout, DS1708TESA/T&R/ application, or DS1708TESA/T&R/ equivalent, key selection criteria include VCC trip point accuracy (3.00–3.15V), NMI timing (200µs pulse, 5µs detection delay), pushbutton debounce integrity, and SOIC-8 package compatibility with legacy MAX707/MAX708 designs.
Technical Context
The DS1708TESA/T&R/ implements a dual-threshold supervision architecture: one comparator monitors VCC directly (trip point 3.00–3.15V) while another compares the IN pin voltage against a 1.25V bandgap reference for early power-fail warning. Its NMI output asserts for ≥200µs when the sensed supply drops below the trip point, with built-in 100µV hysteresis and 5µs noise immunity.
Reset generation is synchronized to both VCC decay and recovery: RST and RST remain active for ≥130ms after VCC returns to tolerance, and PBRST-triggered resets guarantee ≥130ms pulse width regardless of button press duration. The device draws only 50µA at VCC < 3.6V and supports input leakage ≤±1.0µA on IN and PBRST pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Trip Point | 3.00–3.15V (±5% tolerance for 3.3V systems; ensures reliable reset assertion before processor brownout) |
| Reset Pulse Width | ≥130ms (guaranteed minimum active reset duration for full system stabilization on power-up or PBRST event) |
| NMI Pulse Width | ≥200µs (provides deterministic early-warning interrupt before reset activation) |
| IN Trip Reference | 1.20–1.30V (precision bandgap-based threshold enabling flexible external voltage sensing via resistor divider) |
| Supply Current | 50µA max at VCC < 3.6V (ultra-low quiescent current preserves battery life in always-on monitoring) |
| Operating Temp | –40°C to +85°C (industrial-grade thermal range suitable for harsh embedded environments) |
| Package | 8-pin SOIC (150-mil; pin-compatible with MAX707/MAX708, enabling drop-in replacement in existing layouts) |
Pinout & Package
DS1708TESA/T&R/ is supplied in an 8-pin SOIC (150-mil) surface-mount package, compliant with JEDEC MS-012AC, with 1.27mm pitch and 5.0mm × 6.2mm body dimensions.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PBRST | Pushbutton Reset Input | Active-low, internally pulled up (40kΩ typical); debounced and timed to generate ≥130ms RST/RST pulses on release |
| VCC | Power Supply Input | Primary supply rail (1.2–5.5V); powers internal comparators, reference, and output drivers |
| GND | Ground Reference | Return path for all internal circuitry and output loads; must be low-impedance for noise immunity |
| IN | Voltage Sense Input | High-impedance (≤±1.0µA leakage) analog input referenced to 1.25V internal bandgap; enables user-defined power-rail monitoring |
| RST | Active-High Reset Output | CMOS-compatible output asserted high during reset condition; drives microprocessor reset input directly |
| RST | Active-Low Reset Output | Open-drain output asserted low during reset; supports wired-OR configurations and level-shifting |
| NC | No Connect | Unbonded die pad; must be left floating or tied to GND per layout best practices |
| NMI | Non-Maskable Interrupt Output | Open-drain output pulsed low for ≥200µs upon IN voltage crossing trip point; used for preemptive shutdown or logging |
Key Features
| Feature | Design Value |
|---|---|
| Dual Reset Outputs | RST (active-high) and RST (active-low) provide simultaneous compatibility with diverse microprocessor reset architectures without external logic |
| Programmable Voltage Sensing | IN pin + 1.25V internal reference allows precise monitoring of any DC rail (e.g., 5V, 12V, 24V) using external resistor dividers |
| Pushbutton Debounce & Timing | Hardware-based PBRST conditioning eliminates firmware polling or RC filter design, guaranteeing ≥130ms reset pulse on button release |
| Early Power-Fail Warning | NMI output delivers deterministic interrupt ≥200µs before reset activation, enabling time-critical data save or graceful shutdown sequences |
| Industrial Temperature Range | –40°C to +85°C operation ensures reliability in factory automation, telecom infrastructure, and outdoor embedded equipment |
Applications
| Industrial PLC Controller | Telecom Base Station Power Management |
|---|---|
Use Scenario: Monitors 3.3V core supply and 5V I/O rail in programmable logic controllers deployed in factory-floor cabinets with wide ambient temperature swings. IC Role / Device Role / Timing Role: Primary voltage supervisor providing fail-safe reset and NMI-driven watchdog escalation to prevent corrupted ladder logic execution during brownout events. Use Value: Ensures deterministic 130ms reset hold time and 200µs NMI warning pulse - meeting IEC 61131-2 response time requirements for safety-critical control loops. | Use Scenario: Supervises backup battery voltage and main DC-DC converter output in 4G/5G remote radio units operating in unconditioned outdoor enclosures. IC Role / Device Role / Timing Role: Dual-rail monitor using IN pin to sense 12V battery voltage via resistor divider while VCC tracks 3.3V FPGA supply, triggering NMI for battery-switchover sequencing. Use Value: 1.25V reference accuracy and 100µV hysteresis eliminate false NMI triggers from line transients, extending field service life by reducing unnecessary reboots. |
| Medical Diagnostic Imaging Module | Automotive ADAS Camera ECU |
Use Scenario: Secures power integrity for FPGA-based image processing subsystems in portable ultrasound devices powered by Li-ion batteries with variable discharge profiles. IC Role / Device Role / Timing Role: Resets imaging pipeline on VCC droop below 3.00V while using NMI to initiate DRAM flush and sensor shutdown before final power collapse. Use Value: 50µA quiescent current minimizes standby drain; 130ms reset pulse ensures complete FPGA configuration reload after battery recharge cycles. | Use Scenario: Provides fail-safe reset for vision processor SoCs in automotive surround-view camera modules exposed to engine-bay thermal cycling and load-dump transients. IC Role / Device Role / Timing Role: Monitors 3.3V SoC supply and uses PBRST for hardware-initiated reset during firmware update failures or thermal shutdown events. Use Value: SOIC-8 package and MAX707 pin compatibility allow reuse of existing PCB footprints, accelerating AEC-Q100 qualification of new camera generations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage supervisor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX708TESA+ | Same pinout, identical 3.3V ±5% VCC trip (3.00–3.15V), but lacks IN pin and NMI functionality; single-supply-only monitoring | No external voltage sensing or early-warning interrupt capability; limited to VCC-only supervision | Select when only basic 3.3V reset is required and NMI/IN features add unnecessary cost or complexity |
| TPS3808G33DBVR | 3.3V ±2% tighter trip tolerance (3.234–3.366V), 200ms reset timeout, no NMI output, but includes manual reset input and watchdog timer | Higher accuracy and integrated watchdog, but no non-maskable interrupt or dual reset outputs | Select when higher trip-point precision and watchdog supervision outweigh need for NMI-driven pre-reset actions |
Compared with MAX708TESA+, DS1708TESA/T&R/ adds critical IN/NMI capability for predictive power management; compared with TPS3808G33DBVR, it trades tighter trip tolerance for deterministic early-warning interrupt and dual-output flexibility essential in safety-critical industrial systems.
Availability
DS1708TESA/T&R/ is available at Aetrix Electronics and suitable for industrial automation, telecom infrastructure, medical imaging, and automotive ADAS applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for DS1708TESA/T&R/ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for industrial, communications, and computing markets.
The DS1707/DS1708 MicroMonitor product line was engineered to deliver robust, pin-compatible power supervision for microprocessor-based systems where deterministic reset timing, early power-fail warning, and pushbutton interface integrity are mission-critical.
FAQ
What is the exact VCC trip point range for DS1708TESA/T&R/?
The DS1708TESA/T&R/ has a guaranteed VCC trip point range of 3.00V to 3.15V at –40°C to +85°C, corresponding to ±5% tolerance around a nominal 3.3V supply. This specification is validated per the DS1707/DS1708 datasheet Rev. 0, page 7, DC Electrical Characteristics table, row "VCC Trip Point DS1708T". The trip point is temperature-compensated using an internal bandgap reference to maintain accuracy across the full industrial temperature range.
Does DS1708TESA/T&R/ support monitoring voltages other than 3.3V?
Yes, DS1708TESA/T&R/ supports monitoring of any DC voltage via its IN pin, which compares the applied voltage against a precise 1.25V internal reference. Using an external resistor divider (e.g., R1 = 26kΩ, R2 = 10kΩ for 4.5V sensing), users can configure the trip point for rails such as 5V, 12V, or 24V. The DS1708TESA/T&R/ datasheet Figure 5 provides the calculation method, and absolute maximum ratings confirm IN voltage must not exceed VCC.
How does the NMI output of DS1708TESA/T&R/ behave during power-up?
During power-up, the DS1708TESA/T&R/ suppresses NMI generation until VCC reaches its trip point (VCCTP ≈ 3.00–3.15V). This prevents spurious interrupts caused by slow-rising or noisy VCC. Once VCCTP is crossed, the NMI circuit becomes active and will assert a ≥200µs low pulse if the IN pin voltage falls below 1.20–1.30V. The datasheet specifies this behavior in the "Non-Maskable Interrupt" section (page 2) and timing diagram Figure 6.
Is DS1708TESA/T&R/ pin-compatible with MAX707/MAX708 devices?
Yes, DS1708TESA/T&R/ is explicitly pin-compatible with MAX707 and MAX708 in 8-pin SOIC packages, as confirmed in the "Features" section of the datasheet: "Pin compatible with the MAXIM MAX707/MAX708 in 8-pin DIP, 8-pin SOIC packages". Pin functions (PBRST, VCC, GND, IN, RST, RST, NC, NMI) match identically, enabling direct PCB-level replacement without layout changes.
What is the reset timeout duration for DS1708TESA/T&R/ after VCC recovery?
The DS1708TESA/T&R/ guarantees a minimum reset timeout of 130ms after VCC rises above its trip point, as specified in the AC Electrical Characteristics table (page 8) under "Reset Active Time (tRST)". This duration is fixed and independent of VCC slew rate or temperature, ensuring sufficient time for power supply stabilization and microprocessor initialization before release from reset.
DS1708TESA/T&R/ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Power Supply Monitor
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 3.08V
- Output:
- Push-Pull, Totem Pole
- Reset:
- Active High/Active Low
- Reset Timeout:
- 130ms Minimum
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1708TESA/T&R/ FAQ
1.How can I place an order for DS1708TESA/T&R/ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1708TESA/T&R/ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1708TESA/T&R/ reliable?
The price and inventory of DS1708TESA/T&R/ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1708TESA/T&R/ is usually 5 days.
3.What payment methods are accepted for DS1708TESA/T&R/?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1708TESA/T&R/ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1708TESA/T&R/?
DS1708TESA/T&R/ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1708TESA/T&R/ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1708TESA/T&R/?
For technical support, including DS1708TESA/T&R/ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1708TESA/T&R/ requirements.
6.How does Aetrix verify that DS1708TESA/T&R/ is sourced from the original manufacturer or authorized distributors?
All DS1708TESA/T&R/ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1708TESA/T&R/ meets industry standards.
7.What is the process for return or replacement of DS1708TESA/T&R/?
All DS1708TESA/T&R/ units undergo pre-shipment inspection (PSI). If there is an issue with DS1708TESA/T&R/, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1708TESA/T&R/ part is unused and in its original packaging.
Return procedure for DS1708TESA/T&R/:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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