Analog Devices Inc./Maxim Integrated DS1708TESA/T&R
- Part No.:
- DS1708TESA/T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1708TESA/T&R.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,855
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1708TESA/T&R from Maxim Integrated is a 3.3V ±5% precision voltage supervisor IC that monitors VCC, senses external supply voltage via high-impedance IN pin, and debounces pushbutton reset input. It delivers active-low and active-high reset outputs (RST and RST), non-maskable interrupt (NMI), and guarantees ≥130 ms reset pulse width. Used in embedded microprocessor systems requiring reliable power-up sequencing and early power-fail warning.
For engineers reviewing the DS1708TESA/T&R datasheet, DS1708TESA/T&R pinout, DS1708TESA/T&R application, or DS1708TESA/T&R equivalent, key selection criteria include its 3.3V ±5% VCC trip point (3.00–3.15 V), industrial temperature range (−40°C to +85°C), dual reset outputs with 130 ms minimum assertion time, and compatibility with 8-pin SOIC packaging for space-constrained PCB layouts.
Technical Context
The DS1708TESA/T&R implements a precision bandgap-referenced comparator architecture to monitor VCC and an independent high-impedance sense input (IN) referenced to 1.25 V internal threshold. Its NMI output provides early warning of supply decay with 200 µs pulse width and built-in 100 µV hysteresis to reject noise.
It integrates pushbutton debouncing logic with guaranteed 130 ms reset pulse generation upon PBRST release, and features dual complementary reset outputs (RST and RST) asserted during power-down and held active for ≥130 ms after power-up. All functions operate across 1.2 V to 5.5 V supply range with <60 µA quiescent current at VCC < 5.5 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Trip Point | 3.00–3.15 V (±5% tolerance for 3.3 V nominal; ensures accurate reset assertion at defined supply margin) |
| Reset Pulse Width | ≥130 ms (guaranteed minimum duration for reliable processor initialization and stabilization) |
| NMI Pulse Width | ≥200 µs (provides deterministic early-warning signal before reset activation) |
| IN Input Threshold | 1.20–1.30 V (enables flexible external voltage monitoring via resistor divider; supports up to 11.88 V monitored supply) |
| Operating Temperature | −40°C to +85°C (industrial-grade thermal performance for embedded and control applications) |
| Quiescent Current | ≤60 µA at VCC < 5.5 V (minimizes standby power impact in battery-backed or low-power systems) |
| Package | 8-pin SOIC (150-mil width; standard footprint compatible with automated assembly) |
Pinout & Package
DS1708TESA/T&R is housed in an 8-pin SOIC (150-mil) package with exposed pad not present. Pin assignments are standardized across DS1707/DS1708 family variants and validated per Maxim's mechanical drawings.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PBRST | Pushbutton Reset Input | Active-low, internally pulled up (40 kΩ typical); debounced and timed to generate ≥130 ms reset pulse on release |
| VCC | Power Supply Input | Primary supply rail (1.2–5.5 V); powers internal reference, comparators, and output drivers |
| GND | Ground Reference | System ground return for all internal circuitry and I/O pins |
| IN | Voltage Sense Input | High-impedance (≤1 µA leakage) input referenced to 1.25 V internal threshold; enables custom voltage monitoring |
| RST | Active-Low Reset Output | Open-drain output; asserts low during power failure or reset initiation; requires external pull-up |
| RST | Active-High Reset Output | Push-pull output; asserts high during same conditions as RST; no external components needed |
| NC | No Connect | Unbonded pin; must remain unconnected per design; no electrical function |
| NMI | Non-Maskable Interrupt Output | Open-drain output; pulses low for ≥200 µs when IN falls below 1.25 V; used for early power-fail warning |
Key Features
| Feature | Design Value |
|---|---|
| Dual Complementary Reset Outputs | RST (active-low open-drain) and RST (active-high push-pull) simplify interface to diverse microprocessor reset inputs without level-shifting |
| Programmable Voltage Monitoring | IN pin accepts user-defined voltage divider to monitor supplies up to 11.88 V while maintaining 1.25 V internal reference accuracy |
| Debounced Pushbutton Interface | PBRST input eliminates need for external RC debounce circuitry and guarantees ≥130 ms reset pulse regardless of button press duration |
| Early Power-Fail Warning | NMI output provides deterministic 200 µs interrupt pulse before reset activation, enabling graceful shutdown or data save operations |
| Industrial Temperature Operation | Validated −40°C to +85°C performance ensures reliability in harsh environments such as factory automation and outdoor electronics |
Applications
| Industrial PLC Controller | Medical Diagnostic Equipment |
|---|---|
|
Use Scenario: Microcontroller-based programmable logic controller operating in factory environments with fluctuating 24 V DC input converted to 3.3 V. IC Role / Device Role / Timing Role: DS1708TESA/T&R monitors both the 3.3 V rail and upstream 24 V bus via resistor divider on IN pin to detect brownouts before system collapse. Use Value: Dual reset outputs ensure compatibility with legacy and modern MCU reset inputs; NMI enables real-time fault logging prior to forced reset. |
Use Scenario: Portable ultrasound imaging device powered by Li-ion battery with regulated 3.3 V supply and critical data retention requirements. IC Role / Device Role / Timing Role: DS1708TESA/T&R asserts reset during battery voltage sag and triggers NMI to initiate flash memory write completion before power loss. Use Value: 130 ms guaranteed reset hold time allows full CPU shutdown sequence; ≤60 µA ICC minimizes standby drain on battery. |
| Telecom Remote Terminal Unit | Smart Energy Meter |
|
Use Scenario: Outdoor RTU powered by solar-charged battery and PoE, subject to wide ambient temperature swings and intermittent power. IC Role / Device Role / Timing Role: DS1708TESA/T&R supervises 3.3 V logic supply and uses PBRST for manual field reset; NMI alerts host processor of impending brownout. Use Value: −40°C to +85°C rating ensures operation in unheated enclosures; 8-pin SOIC fits compact PCB layout with minimal BOM count. |
Use Scenario: ANSI C12.20-compliant electricity meter with tamper detection, real-time clock backup, and firmware update capability. IC Role / Device Role / Timing Role: DS1708TESA/T&R monitors main 3.3 V rail and generates NMI to trigger secure RTC save and firmware rollback on detected supply anomaly. Use Value: Precision ±5% VCC trip point (3.00–3.15 V) aligns with metering SoC reset thresholds; dual RST outputs support redundant safety logic paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage supervisor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6326UT46D3+T | Single active-low reset output; 4.63 V fixed trip point; no NMI or IN sense pin; SOT23-3 package | Lacks voltage monitoring flexibility and early-warning interrupt; suited only for basic 5 V reset supervision | Select when only simple 5 V reset is required and board space is extremely constrained |
| TPS3808G33DBVR | 3.3 V ±2% trip point; adjustable reset timeout (1.25 ms to 10 s); no NMI output; 5-pin SOT23 package | Higher trip accuracy but no early-warning interrupt or external voltage sense; reset timing configurable via capacitor | Choose when tighter VCC tolerance is critical and NMI functionality is unnecessary |
Compared with MAX6326UT46D3+T and TPS3808G33DBVR, DS1708TESA/T&R uniquely combines 3.3 V ±5% supervision, dual complementary reset outputs, NMI early-warning interrupt, and user-programmable IN voltage sensing - making it optimal for systems requiring layered power-fail response and flexible supply monitoring.
Availability
DS1708TESA/T&R is available at Aetrix Electronics and suitable for industrial PLC controllers, medical diagnostic equipment, telecom remote terminal units, smart energy meters, and other applications requiring stable component supply with guaranteed long-term availability.
Supply support for DS1708TESA/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for demanding industrial, automotive, and communications applications.
The DS1707/DS1708 family was engineered to provide robust, multi-function power supervision for microprocessor-based systems-integrating reset generation, pushbutton control, and early power-fail warning in a single 8-pin package.
FAQ
What is the exact VCC trip point range for DS1708TESA/T&R?
The DS1708TESA/T&R has a guaranteed VCC trip point range of 3.00 V to 3.15 V, corresponding to ±5% tolerance around a nominal 3.3 V supply. This specification is validated over the full −40°C to +85°C operating temperature range and is documented in the DC Electrical Characteristics table of the official Maxim datasheet. The DS1708TESA/T&R uses an internal temperature-compensated bandgap reference to maintain this accuracy across voltage and temperature variations.
Does DS1708TESA/T&R support monitoring of voltages higher than 3.3 V?
Yes, DS1708TESA/T&R supports monitoring of higher voltages via its IN pin, which has a fixed 1.25 V internal threshold. By using an external resistor divider (e.g., R1 = 26 kΩ, R2 = 10 kΩ), the DS1708TESA/T&R can safely monitor supplies up to 11.88 V while maintaining accuracy. The IN pin is high-impedance (<1 µA leakage), minimizing loading on the monitored circuit, and the voltage at IN must not exceed VCC to prevent damage.
How does the NMI output of DS1708TESA/T&R differ from the RST outputs?
The NMI output of DS1708TESA/T&R provides an early-warning signal (≥200 µs low pulse) when the IN pin voltage drops below 1.25 V, occurring before RST/RST assertion. In contrast, RST and RST are system reset signals activated when VCC falls below its trip point (3.00–3.15 V) and held active for ≥130 ms. This staged response allows DS1708TESA/T&R to enable graceful shutdown or data save operations before hard reset.
Is DS1708TESA/T&R pin-compatible with other devices in the DS1707/DS1708 family?
Yes, DS1708TESA/T&R is pin-compatible with all members of the DS1707/DS1708 family in the same package type-including DS1707ESA, DS1708ESA, DS1708RESA, and DS1708SESA-sharing identical 8-pin SOIC (150-mil) pinout, terminal functions, and PCB footprint. This allows direct substitution within the same voltage-monitoring configuration without layout changes.
What is the reset pulse width guarantee for DS1708TESA/T&R during pushbutton operation?
DS1708TESA/T&R guarantees a minimum reset pulse width of 130 ms when triggered by the PBRST pin, measured from the moment the pushbutton is released (PBRST transitions from low to high). This timing is internally generated and independent of button press duration or contact bounce, eliminating the need for external RC debounce networks. The same 130 ms minimum applies to power-up and power-down reset assertion.
DS1708TESA/T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- MicroMonitor™
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 3.08V
- Output:
- Push-Pull, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- 130ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1708TESA/T&R FAQ
1.How can I place an order for DS1708TESA/T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1708TESA/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1708TESA/T&R reliable?
The price and inventory of DS1708TESA/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1708TESA/T&R is usually 5 days.
3.What payment methods are accepted for DS1708TESA/T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1708TESA/T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1708TESA/T&R?
DS1708TESA/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1708TESA/T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1708TESA/T&R?
For technical support, including DS1708TESA/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1708TESA/T&R requirements.
6.How does Aetrix verify that DS1708TESA/T&R is sourced from the original manufacturer or authorized distributors?
All DS1708TESA/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1708TESA/T&R meets industry standards.
7.What is the process for return or replacement of DS1708TESA/T&R?
All DS1708TESA/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1708TESA/T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1708TESA/T&R part is unused and in its original packaging.
Return procedure for DS1708TESA/T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1708TESA/T&R Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
