Analog Devices Inc./Maxim Integrated DS1817R-20+T&R

Overview

DS1817R-20+T&R from Maxim Integrated (now Analog Devices) is a precision voltage-monitoring supervisory IC that provides active-high reset signaling for microprocessors in 3.0V systems. It features a 20% V_CC trip point (2.47–2.64V), 150ms reset pulse width, push-pull output, and operates from –40°C to +85°C in SOT-23 package.

For engineers reviewing the DS1817R-20+T&R datasheet, DS1817R-20+T&R pinout, DS1817R-20+T&R application, or DS1817R-20+T&R equivalent, key selection criteria include guaranteed reset timing after power-up/power-down, tolerance-matched trip threshold for 3.0V rails, and compatibility with space-constrained PCB layouts requiring SOT-23 footprint.

Technical Context

The DS1817R-20+T&R integrates a temperature-compensated voltage reference and comparator to detect V_CC deviations beyond ±20% of nominal 3.0V. Its internal circuitry asserts RST high on out-of-tolerance detection and holds it active for 100–250ms after V_CC recovery, ensuring processor stabilization.

It uses CMOS output stage with VOH ≥ V_CC–0.5V and IOL = +10mA, supporting direct interface to TTL/CMOS inputs without pull-up resistors. The device draws only 28–35µA quiescent current and tolerates V_CC up to 5.5V, enabling use across mixed-voltage designs.

Key Specifications

Pinout & Package

SOT-23-3 surface-mount package with 1.3mm × 2.9mm footprint and 0.95mm height; RoHS-compliant, lead-free finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage-monitoring reset applications.

Compared with TPS3808G18DBVR and MAX6326UT29D3+, the DS1817R-20+T&R offers optimal balance of 3.0V-system specificity, ±20% hysteresis margin, and minimal BOM count-making it ideal where cost, footprint, and rail-matched reliability outweigh fine-grained adjustability.

Availability

DS1817R-20+T&R is available at Aetrix Electronics and suitable for industrial control, medical sensing, point-of-sale terminals, and smart metering applications requiring stable component supply and long-term manufacturability.

Supply support for DS1817R-20+T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices (via acquisition of Maxim Integrated) designs precision analog, mixed-signal, and power management ICs for industrial, automotive, and communications markets.

The DS1817R-20+T&R belongs to Maxim's EconoReset™ family-engineered for cost-sensitive, space-constrained applications needing reliable, single-rail power supervision without design overhead.

FAQ

What is the exact V_CC trip voltage range for DS1817R-20+T&R?

The DS1817R-20+T&R has a guaranteed V_CC trip point between 2.47V and 2.64V at –40°C to +85°C. This ±20% window around 3.0V ensures reliable detection of brownout conditions specific to 3.0V logic systems, and is factory-trimmed using temperature-compensated reference circuitry inside the DS1817R-20+T&R.

Does DS1817R-20+T&R require an external pull-up resistor on the RST pin?

No. The DS1817R-20+T&R features a push-pull CMOS output stage, so the RST pin actively drives high and low without external components. This eliminates the need for a pull-up resistor, reduces BOM count, and ensures clean signal edges-key for noise-immune reset signaling in the DS1817R-20+T&R.

Can DS1817R-20+T&R be used with a 3.3V supply rail?

Yes. While optimized for 3.0V systems, the DS1817R-20+T&R accepts V_CC up to 5.5V and draws only 35µA. When monitoring a 3.3V rail, its 2.47–2.64V trip window still provides valid undervoltage detection-but note that this corresponds to ~21–20% sag, not the nominal 20% of 3.3V. The DS1817R-20+T&R remains functional and stable in such configurations.

What is the reset timeout behavior during power-down versus power-up for DS1817R-20+T&R?

During both power-down and power-up, the DS1817R-20+T&R asserts RST within 2–5µs of V_CC crossing the trip threshold. After V_CC returns to tolerance, RST remains active for 100–250ms (typ. 150ms). This identical timing ensures consistent processor initialization regardless of fault direction-critical for deterministic behavior in the DS1817R-20+T&R.

Is DS1817R-20+T&R compatible with SOT-23 PCB footprints from other reset ICs?

Yes-the DS1817R-20+T&R uses standard SOT-23-3 footprint (JEDEC MO-178AA) with 0.95mm pitch and 1.3×2.9mm body. Pin 1 (RST), Pin 2 (V_CC), and Pin 3 (GND) match industry-standard assignments. However, electrical compatibility depends on trip point and output type; verify against target system's voltage and interface requirements before substituting into existing layout for DS1817R-20+T&R.