Analog Devices Inc./Maxim Integrated DS1830AS+T&R
- Part No.:
- DS1830AS+T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1830AS+T&R.pdf
- Description:
- IC SUPERVISOR 3 CHANNEL 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1830AS+T&R from Maxim Integrated is a 3.3V triple-output reset sequencer IC that monitors VCC for out-of-tolerance conditions and generates time-sequenced active-low reset signals (RST1, RST2, RST3) with programmable delays (10/20/50 ms min for RST1), precision voltage trip points (2.47–3.15 V depending on TOL setting), and pushbutton override capability. It operates from -40°C to +85°C in 8-pin SO package and is used in multi-rail embedded systems requiring controlled power-up sequencing.
For engineers reviewing the DS1830AS+T&R datasheet, DS1830AS+T&R pinout, DS1830AS+T&R application, or DS1830AS+T&R equivalent, key selection criteria include its 3.3V-specific VCC trip thresholds, TD-selectable reset timing ratios (1×/5×/10×), open-drain outputs, internal 40kΩ PBRST pull-up, and tolerance-selectable trip point accuracy (±0.13 V typical).
Technical Context
The DS1830AS+T&R implements a precision temperature-compensated bandgap reference and comparator to detect VCC deviations against three selectable trip thresholds (2.47–3.15 V), sampled only while VCC remains below the lowest trip value. Its internal oscillator drives a clock chain that generates fixed timing ratios between RST1, RST2, and RST3 - with RST2 always 5× and RST3 always 10× the RST1 delay determined by TD state (GND/N.C./VCC).
Reset assertion occurs within 5–8 µs of VCC crossing the trip threshold; release follows a sequenced timeout after VCC returns in-tolerance. The PBRST input supports manual reset initiation via ≥1ms low pulse, debounced internally, and forces all outputs active until released - then resumes TD-based sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Trip Range | 2.47 V to 3.15 V (selectable via TOL pin: GND/NC/VCC) |
| RST1 Minimum Delay | 10 ms / 20 ms / 50 ms (TD = GND / NC / VCC) |
| RST Timing Ratio | RST2 = 5× RST1; RST3 = 10× RST1 (fixed ratio, no external components) |
| Supply Voltage Range | 1.0 V to 5.5 V (supports wide-input biasing; rated for 3.3 V operation) |
| Operating Temperature | -40°C to +85°C (fully specified for industrial environments) |
| Standby Current | 10 µA to 25 µA (enables ultra-low-power system monitoring) |
| PBRST Input | Internally pulled up to VCC with 40 kΩ; debounced; ≥1 ms low pulse required |
Pinout & Package
DS1830AS+T&R is supplied in an 8-pin SOIC (SO-8, 150-mil width) package with standard JEDEC MS-012AC footprint and 1.27 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - PBRST | Pushbutton Reset Input | Active-low manual reset trigger; internally pulled up to VCC (40 kΩ); ≥1 ms low pulse initiates sequenced reset |
| 2 - TD | Time Delay Select Input | Configures RST1 base delay: GND = 10 ms, NC = 20 ms, VCC = 50 ms; sets RST2/RST3 as exact multiples |
| 3 - TOL | VCC Tolerance Select Input | Selects trip threshold: GND = 2.80–2.97 V, NC = 2.47–2.64 V, VCC = 2.98–3.15 V (for DS1830A) |
| 4 - GND | Ground Reference | Analog/digital ground return for internal reference and comparator circuitry |
| 5 - RST3 | Reset Output 3 | Open-drain, active-low output; releases last in sequence (10× RST1 delay); requires external pull-up |
| 6 - RST2 | Reset Output 2 | Open-drain, active-low output; releases second (5× RST1 delay); requires external pull-up |
| 7 - RST1 | Reset Output 1 | Open-drain, active-low output; releases first (base delay); requires external pull-up |
| 8 - VCC | Power Supply Input | Primary supply rail (1.0–5.5 V); powers internal reference, comparator, oscillator, and logic |
Key Features
| Feature | Design Value |
|---|---|
| Triple sequenced reset outputs | RST1 → RST2 → RST3 release order eliminates race conditions during multi-rail power-up |
| Programmable VCC trip thresholds | Three precise, temperature-compensated trip points (2.47–3.15 V) selected via single TOL pin |
| TD-selectable timing architecture | Single pin configures three distinct RST1 base delays (10/20/50 ms), with RST2/RST3 automatically scaled |
| Integrated pushbutton interface | Internal 40 kΩ pull-up and debounce eliminate external RC network and reduce BOM count |
| Ultra-low standby current | 10–25 µA operation enables use in battery-backed or energy-sensitive monitoring circuits |
Applications
| Industrial PLC Controller | Medical Diagnostic Imaging System |
|---|---|
Use Scenario: Power-up of FPGA, microcontroller, and analog front-end ASIC from independent 3.3V, 2.5V, and 1.8V rails. IC Role / Device Role / Timing Role: DS1830AS+T&R acts as primary reset sequencer, asserting RST1 to FPGA configuration logic, RST2 to MCU core, and RST3 to ADC/DAC subsystems. Use Value: Ensures FPGA config completes before MCU boot and analog subsystem initialization, preventing metastability and lockup. | Use Scenario: Cold start of MRI signal processing board with high-precision ADCs, DSPs, and memory controllers. IC Role / Device Role / Timing Role: DS1830AS+T&R provides synchronized, staggered reset release timed to match analog power stabilization and digital core wake-up latency. Use Value: Eliminates need for discrete RC timers and reduces risk of partial initialization causing data corruption in safety-critical imaging paths. |
| Automotive Infotainment Head Unit | Telecom Baseband Processing Module |
Use Scenario: Multi-voltage domain startup (3.3V SoC, 1.2V core, 1.8V I/O) under automotive cold-crank conditions (-40°C to +85°C). IC Role / Device Role / Timing Role: DS1830AS+T&R monitors 3.3V rail and sequences resets to SoC, PMIC, and audio codec - with TD set to NC for 20 ms base delay. Use Value: Guarantees stable 3.3V rail before releasing SoC reset, avoiding brownout-induced boot failure during engine cranking. | Use Scenario: Power-on of LTE baseband processor, RF transceiver, and DDR3 memory controller in compact telecom module. IC Role / Device Role / Timing Role: DS1830AS+T&R serves as centralized reset manager, using TOL=VCC for tight 2.98–3.15 V trip and TD=GND for fast 10 ms RST1. Use Value: Enables rapid, deterministic boot sequence compliant with 3GPP power-up timing requirements for cellular modems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar reset sequencer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6326UT29D3+ | Single-output, 2.93 V fixed trip, no TD/TOL programming; 140 ms min reset pulse | Lacks sequencing and voltage/timing flexibility; suited only for simple single-rail reset | Choose when only basic 3.3V reset is needed and board space is constrained |
| TPS3808G33DBVR | Single-output, 3.3 V fixed trip, adjustable delay (1 ms–10 s) via external capacitor; no sequencing | No RST2/RST3 outputs; requires external cap for timing; no TOL select | Prefer when variable delay is critical but multi-output sequencing is unnecessary |
Compared with MAX6326UT29D3+ and TPS3808G33DBVR, the DS1830AS+T&R uniquely delivers three precisely ratioed, programmable reset outputs in a single 8-pin SO package - eliminating discrete timing networks and enabling deterministic multi-rail power sequencing without firmware intervention.
Availability
DS1830AS+T&R is available at Aetrix Electronics and suitable for industrial control systems, medical imaging devices, automotive infotainment units, and telecom baseband modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for DS1830AS+T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for industrial, medical, automotive, and communications applications.
The DS1830AS+T&R belongs to Maxim's reset and supervisory IC product line, engineered specifically for reliable, hardware-based power-up sequencing in multi-rail embedded systems where deterministic timing and voltage margining are critical.
FAQ
What is the function of the TOL pin on the DS1830AS+T&R?
The TOL pin on the DS1830AS+T&R selects one of three VCC trip thresholds: 2.47–2.64 V (TOL open), 2.80–2.97 V (TOL grounded), or 2.98–3.15 V (TOL tied to VCC). This selection is latched during power-up before VCC exceeds the lowest trip value and cannot be changed dynamically. The DS1830AS+T&R uses this setting to configure its precision voltage monitor for 3.3V system operation.
How does the TD pin affect reset timing in the DS1830AS+T&R?
The TD pin configures the base delay for RST1: 10 ms (TD = GND), 20 ms (TD = open), or 50 ms (TD = VCC). RST2 and RST3 are then automatically set to exactly 5× and 10× that base delay, respectively. This fixed-ratio architecture ensures consistent sequencing without external components. The DS1830AS+T&R maintains these timing relationships across temperature and supply voltage variations.
Can the DS1830AS+T&R be used in a 5V system?
No - the DS1830AS+T&R is specifically designed and characterized for 3.3V systems, with trip thresholds ranging from 2.47 V to 3.15 V. For 5V applications, the pin-compatible DS1830S or DS1830U (non-A variants) must be used, as they provide 4.00–4.74 V trip points. Using DS1830AS+T&R in a 5V system would result in immediate, continuous reset assertion due to VCC exceeding all trip thresholds.
What is the maximum sink current capability of each reset output on the DS1830AS+T&R?
Each reset output (RST1, RST2, RST3) on the DS1830AS+T&R can sink up to 20 mA when pulled to 0.4 V, per the DC electrical characteristics table. This allows direct interfacing with standard logic inputs (e.g., microcontroller nRESET pins) using typical 4.7 kΩ pull-up resistors. The DS1830AS+T&R specifies this drive strength across the full -40°C to +85°C operating range.
Is the DS1830AS+T&R pin-compatible with other packages in the DS1830 family?
Yes - the DS1830AS+T&R (8-pin SO) shares identical pinout and functionality with the DS1830A (8-pin DIP) and DS1830AU (8-pin µSOP). All three variants use the same pin assignment: PBRST (1), TD (2), TOL (3), GND (4), RST3 (5), RST2 (6), RST1 (7), VCC (8). This enables drop-in replacement across form factors without PCB redesign, provided mechanical constraints allow the SOIC footprint.
DS1830AS+T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 3
- Voltage - Threshold:
- 3.3V
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 10ms; 20ms; 50ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1830AS+T&R FAQ
1.How can I place an order for DS1830AS+T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1830AS+T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1830AS+T&R reliable?
The price and inventory of DS1830AS+T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1830AS+T&R is usually 5 days.
3.What payment methods are accepted for DS1830AS+T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1830AS+T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1830AS+T&R?
DS1830AS+T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1830AS+T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1830AS+T&R?
For technical support, including DS1830AS+T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1830AS+T&R requirements.
6.How does Aetrix verify that DS1830AS+T&R is sourced from the original manufacturer or authorized distributors?
All DS1830AS+T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1830AS+T&R meets industry standards.
7.What is the process for return or replacement of DS1830AS+T&R?
All DS1830AS+T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1830AS+T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1830AS+T&R part is unused and in its original packaging.
Return procedure for DS1830AS+T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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