Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Analog Devices Inc./Maxim Integrated DS1831BS/T&R

Name: DS1831BS/T&R
Brand: Analog Devices Inc./Maxim Integrated
SKU: DS1831BS/T&R
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: DS1831BS/T&R

Manufacturer:: Analog Devices Inc./Maxim Integrated

Category:: Supervisors

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: DS1831BS/T&R.pdf

Description:: IC SUPERVISOR 4 CHANNEL 16SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,127

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

DS1831BS/T&R from Maxim Integrated is a multisupply voltage monitor IC with dual open-drain reset outputs (RST5V, RST3.3V), two user-configurable sense inputs (IN1, IN2), and pushbutton status output (PBST). It monitors 5V and 3.3V supplies with selectable tolerances (5%/10%/20%), configurable reset delays (10ms/100ms/1s), and operates from −40°C to +85°C. Used in embedded systems requiring reliable power sequencing and fault detection during brownout or startup.

For engineers reviewing the DS1831BS/T&R datasheet, DS1831BS/T&R pinout, DS1831BS/T&R application, or DS1831BS/T&R equivalent, this page delivers verified electrical parameters, validated pin functions, confirmed tolerance and delay configurations, and real-world use cases for multi-rail industrial controllers, telecom power modules, and FPGA-based platforms with manual reset traceability.

Technical Context

The DS1831BS/T&R implements dual independent voltage comparators referenced to a precision 1.25V temperature-compensated bandgap, enabling accurate monitoring of IN5V and IN3.3V against programmable trip points. TOL5V and TOL3.3V pins configure input tolerance (5%, 10%, or 20%), while TD5V and TD3.3V select reset hold times (10ms, 100ms, or 1s) via discrete logic levels (GND/float/VCC).

Unlike the DS1831A (watchdog-enabled) or base DS1831, the DS1831BS replaces the master pushbutton reset (MPBRST) with PBST - an open-drain output that latches the status of the most recent reset event triggered by the master pushbutton. Internal power is drawn from the higher of IN5V or IN3.3V, and valid operation requires ≥1.0V on at least one supply input.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Inputs	IN5V (1.0–5.5V) and IN3.3V (1.0–5.5V); device draws internal power from higher of the two
Reset Outputs	RST5V and RST3.3V - open-drain, active-low, require external pull-up resistors (e.g., 10kΩ)
Tolerance Selection	TOL5V/TOL3.3V: 5% (tied to supply), 10% (GND), or 20% (floating) - set at power-up only
Reset Delay Options	TD5V/TD3.3V: 10ms (GND), 100ms (float), or 1s (VCC) - fixed after power-on
Pushbutton Status	PBST: open-drain latch indicating last reset was initiated by MPBRST; requires external pull-up
Operating Temp	−40°C to +85°C - qualified for industrial-grade embedded and telecom equipment
Package	16-pin SOIC (150mil width), tape-and-reel (T&R) - RoHS-compliant, JEDEC-standard footprint

Pinout & Package

DS1831BS/T&R is supplied in a 16-pin SOIC package (150mil width, 1.27mm pitch), optimized for automated SMT assembly and space-constrained PCB layouts. Pin compatibility matches DS1831S and DS1831AS footprints.

Pin/Terminal	Circuit Role	Design Meaning
IN5V	5V supply input	Primary power source; used for internal bias and trip point reference; must be ≥1.0V for operation
IN3.3V	3.3V supply input	Secondary power source; internal power selected from higher of IN5V or IN3.3V
RST5V	5V reset output	Open-drain, active-low signal asserting processor reset when IN5V falls outside tolerance
RST3.3V	3.3V reset output	Open-drain, active-low signal asserting reset when IN3.3V falls outside tolerance
TOL5V	5V tolerance select	Configures IN5V trip point: 5% (IN5V), 10% (GND), or 20% (float); latched at power-up
TOL3.3V	3.3V tolerance select	Configures IN3.3V trip point: 5% (IN3.3V), 10% (GND), or 20% (float); latched at power-up
TD5V	5V reset delay select	Sets RST5V hold time: 10ms (GND), 100ms (float), or 1s (VCC)
TD3.3V	3.3V reset delay select	Sets RST3.3V hold time: 10ms (GND), 100ms (float), or 1s (VCC)
PBRST5V	5V pushbutton reset input	Pull-to-GND initiates manual reset of RST5V; internally pulled up to IN5V via 100kΩ
PBRST3.3V	3.3V pushbutton reset input	Pull-to-GND initiates manual reset of RST3.3V; internally pulled up to IN3.3V via 100kΩ
IN1 / IN2	User-configurable sense inputs	Compare against 1.25V reference; generate NMI1/NMI2 pulses if input <1.25V (hysteresis = 100µV)
PBST	Pushbutton status output	Open-drain latch: low = last reset was master pushbutton event; high = cleared by non-MPBRST reset
GND	Ground reference	Common return path for all analog and digital circuitry; required for comparator accuracy

Key Features

Feature	Design Value
Dual independent supply monitoring	Simultaneous 5V and 3.3V supervision with separate reset outputs and tolerance/delay configuration
Master pushbutton status latching	PBST output retains state of most recent MPBRST-triggered reset, enabling firmware-level diagnostic logging
Configurable trip tolerances	Three tolerance options per supply (5%/10%/20%) selected without external components - reduces BOM count
Programmable reset timing	Three discrete delay values (10ms/100ms/1s) per reset output, set via simple logic-level connections
Two auxiliary voltage monitors	IN1 and IN2 sense arbitrary voltages using external resistor dividers; referenced to stable 1.25V bandgap
Industrial temperature range	−40°C to +85°C operation ensures reliability in uncontrolled environments like base stations and PLCs

Applications

Industrial PLC Power Sequencing	Telecom Line Card Supervision
Use Scenario: A programmable logic controller uses separate 5V logic and 3.3V I/O rails, requiring coordinated reset assertion during cold start and brownout. IC Role / Device Role / Timing Role: DS1831BS/T&R acts as centralized power supervisor, generating synchronized RST5V and RST3.3V signals with independently configured delays to ensure FPGA config completes before microcontroller boot. Use Value: Eliminates need for discrete RC timers and dual-reset ICs; PBST enables diagnostics to distinguish operator-initiated resets from power faults.	Use Scenario: A telecom line card with multiple ASICs powered from 5V, 3.3V, and 1.8V rails must detect undervoltage on primary supplies and trigger graceful shutdown. IC Role / Device Role / Timing Role: DS1831BS/T&R monitors IN5V and IN3.3V, while IN1 senses 1.8V rail via resistor divider; asserts resets and latches PBST to flag manual maintenance events. Use Value: Single-chip solution replaces three discrete supervisors; tolerance flexibility accommodates aging power supply drift without redesign.
FPGA-Based Test Equipment	Medical Diagnostic Controller
Use Scenario: Benchtop test equipment uses FPGA, ARM core, and analog front-end, each with distinct power-up timing requirements and safety-critical reset coordination. IC Role / Device Role / Timing Role: DS1831BS/T&R provides sequenced RST5V (100ms) and RST3.3V (10ms) to align FPGA configuration with processor initialization; PBST logs technician-initiated recalibration resets. Use Value: Configurable delays avoid race conditions; open-drain outputs interface cleanly with mixed-voltage FPGA I/O banks.	Use Scenario: A portable ultrasound controller requires fail-safe power monitoring across battery-backed 3.3V and USB-derived 5V rails, with audit-trail capability for regulatory compliance. IC Role / Device Role / Timing Role: DS1831BS/T&R supervises both rails and logs reset origin via PBST; NMI1 monitors backup battery voltage to preempt low-power shutdown. Use Value: Latched PBST satisfies FDA 21 CFR Part 11 electronic record requirements; −40°C to +85°C rating supports field-deployable operation.

Industrial PLC Power Sequencing

Telecom Line Card Supervision

Use Scenario: A programmable logic controller uses separate 5V logic and 3.3V I/O rails, requiring coordinated reset assertion during cold start and brownout.

IC Role / Device Role / Timing Role: DS1831BS/T&R acts as centralized power supervisor, generating synchronized RST5V and RST3.3V signals with independently configured delays to ensure FPGA config completes before microcontroller boot.

Use Value: Eliminates need for discrete RC timers and dual-reset ICs; PBST enables diagnostics to distinguish operator-initiated resets from power faults.

Use Scenario: A telecom line card with multiple ASICs powered from 5V, 3.3V, and 1.8V rails must detect undervoltage on primary supplies and trigger graceful shutdown.

IC Role / Device Role / Timing Role: DS1831BS/T&R monitors IN5V and IN3.3V, while IN1 senses 1.8V rail via resistor divider; asserts resets and latches PBST to flag manual maintenance events.

Use Value: Single-chip solution replaces three discrete supervisors; tolerance flexibility accommodates aging power supply drift without redesign.

FPGA-Based Test Equipment

Medical Diagnostic Controller

Use Scenario: Benchtop test equipment uses FPGA, ARM core, and analog front-end, each with distinct power-up timing requirements and safety-critical reset coordination.

IC Role / Device Role / Timing Role: DS1831BS/T&R provides sequenced RST5V (100ms) and RST3.3V (10ms) to align FPGA configuration with processor initialization; PBST logs technician-initiated recalibration resets.

Use Value: Configurable delays avoid race conditions; open-drain outputs interface cleanly with mixed-voltage FPGA I/O banks.

Use Scenario: A portable ultrasound controller requires fail-safe power monitoring across battery-backed 3.3V and USB-derived 5V rails, with audit-trail capability for regulatory compliance.

IC Role / Device Role / Timing Role: DS1831BS/T&R supervises both rails and logs reset origin via PBST; NMI1 monitors backup battery voltage to preempt low-power shutdown.

Use Value: Latched PBST satisfies FDA 21 CFR Part 11 electronic record requirements; −40°C to +85°C rating supports field-deployable operation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multisupply monitoring applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
DS1831S/T&R	No PBST output; includes MPBRST pin instead; identical pinout and tolerance/delay configuration	Lacks reset origin tracking; suitable where manual reset is transient and not logged	Select DS1831S/T&R if system firmware does not require distinction between power-fault and operator-initiated resets.
MAX6369ESA+	Single-supply (3.3V only) supervisor with watchdog, no dual-rail monitoring or PBST	Cannot monitor both 5V and 3.3V simultaneously; lacks auxiliary sense inputs and master pushbutton status	Choose MAX6369ESA+ only for cost-sensitive 3.3V-only designs where watchdog suffices and dual-rail supervision is unnecessary.

Compared with DS1831S/T&R, DS1831BS/T&R trades MPBRST functionality for PBST latching-enabling deterministic reset forensics without adding external storage. Against MAX6369ESA+, DS1831BS/T&R delivers true dual-rail supervision and flexible tolerance/delay selection, making it irreplaceable in systems requiring coordinated 5V/3.3V power management with audit capability.

Availability

DS1831BS/T&R is available at Aetrix Electronics and suitable for industrial automation, telecom infrastructure, and medical electronics requiring stable component supply, long-term lifecycle support, and RoHS-compliant tape-and-reel packaging.

Supply support for DS1831BS/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for power management, sensing, and interface applications in industrial, automotive, and communications markets.

The DS1831BS/T&R belongs to Maxim's Micromonitor™ family of power-supply supervisors, engineered specifically for robust, multi-rail voltage monitoring in space- and reliability-constrained embedded systems.

FAQ

What is the function of the PBST pin on the DS1831BS/T&R?

The PBST pin on the DS1831BS/T&R is an open-drain output that latches the status of the most recent reset event caused by the master pushbutton (MPBRST). When the last reset originated from MPBRST, PBST remains low until cleared by any other reset source (e.g., power fault or PBRST5V). This enables firmware to distinguish operator-initiated resets from power-related failures - a key diagnostic feature unique to the DS1831BS/T&R among the DS1831 family.

Can the DS1831BS/T&R monitor voltages other than 5V and 3.3V?

Yes. The DS1831BS/T&R includes two auxiliary sense inputs - IN1 and IN2 - each referenced to its internal 1.25V precision bandgap. By using external resistor dividers, users can scale higher voltages (e.g., 12V, 24V) down to the 1.25V threshold, allowing detection of out-of-tolerance conditions on arbitrary rails. The DS1831BS/T&R does not provide dedicated outputs for these inputs but can assert NMI1/NMI2 pulses or drive them into PBRST5V/PBRST3.3V to trigger automatic resets.

How are tolerance and reset delay configured on the DS1831BS/T&R?

Tolerance is set per supply using TOL5V and TOL3.3V pins: connecting to the respective supply yields 5%, to GND yields 10%, and leaving floating yields 20%. Reset delay is set per output using TD5V and TD3.3V pins: GND selects 10ms, floating selects 100ms, and VCC selects 1s. These configurations are sampled once at power-up and remain fixed until the next power cycle - no runtime reconfiguration is supported on the DS1831BS/T&R.

Does the DS1831BS/T&R require external pull-up resistors on its reset outputs?

Yes. Both RST5V and RST3.3V are open-drain outputs and require external pull-up resistors to establish a valid high state when inactive. A typical value is 10kΩ connected to the corresponding supply rail (e.g., RST5V pulled to 5V, RST3.3V pulled to 3.3V). The DS1831BS/T&R does not include internal pull-ups on these outputs, and omission results in undefined logic levels and potential system boot failure.

What is the minimum supply voltage required for the DS1831BS/T&R to operate?

The DS1831BS/T&R requires at least 1.0V on either IN5V or IN3.3V to maintain functional outputs; however, accurate voltage monitoring requires at least one of those inputs to be ≥1.5V. If both are below 1.5V but ≥1.0V, all outputs remain asserted (active-low) - a fail-safe behavior ensuring system reset under marginal supply conditions. This specification is explicitly defined in the DS1831BS/T&R's Recommended DC Operating Conditions table.

DS1831BS/T&R Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc./Maxim Integrated

Series:: MicroMonitor™

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Multi-Voltage Supervisor

Number of Voltages Monitored:: 4

Voltage - Threshold:: 3.3V, 5V, Adj, Adj

Output:: Open Drain or Open Collector

Reset:: Active Low

Reset Timeout:: 10ms; 100ms; 1,000ms Minimum

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

DS1831BS/T&R FAQ

1.How can I place an order for DS1831BS/T&R through Aetrix?

Please submit a Request for Quotation (RFQ) for DS1831BS/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for DS1831BS/T&R reliable?

The price and inventory of DS1831BS/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1831BS/T&R is usually 5 days.

3.What payment methods are accepted for DS1831BS/T&R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1831BS/T&R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for DS1831BS/T&R?

DS1831BS/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your DS1831BS/T&R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for DS1831BS/T&R?

For technical support, including DS1831BS/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1831BS/T&R requirements.

6.How does Aetrix verify that DS1831BS/T&R is sourced from the original manufacturer or authorized distributors?

All DS1831BS/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1831BS/T&R meets industry standards.

7.What is the process for return or replacement of DS1831BS/T&R?

All DS1831BS/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1831BS/T&R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The DS1831BS/T&R part is unused and in its original packaging.

Return procedure for DS1831BS/T&R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…