Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Analog Devices Inc./Maxim Integrated DS1831DS+T&R

Name: DS1831DS+T&R
Brand: Analog Devices Inc./Maxim Integrated
SKU: DS1831DS+T&R
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: DS1831DS+T&R

Manufacturer:: Analog Devices Inc./Maxim Integrated

Category:: Supervisors

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: DS1831DS+T&R.pdf

Description:: IC SUPERVISOR 4 CHANNEL 16SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,662

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

DS1831DS+T&R from Maxim Integrated is a 2.5V/3.3V multisupply micro-monitor IC with integrated watchdog timer, dual voltage supervision (IN2.5V and IN3.3V), open-drain reset outputs (RST2.5V and RST3.3V), user-configurable tolerance (5%/10%/20%), and selectable reset delays (10ms/100ms/1s). It draws internal power from the higher of the two supply inputs and operates from -40°C to +85°C in embedded power management systems.

For engineers reviewing the DS1831DS+T&R datasheet, DS1831DS+T&R pinout, DS1831DS+T&R application, or DS1831DS+T&R equivalent, this device supports precise multi-rail monitoring with watchdog supervision, pushbutton override, and NMI-capable sense inputs for upstream voltage fault detection in industrial controllers and telecom power systems.

Technical Context

The DS1831DS+T&R implements two independent precision voltage comparators referenced to a 1.25V temperature-compensated bandgap, each with dedicated TOL and TD pins for tolerance and delay configuration. Its watchdog function (enabled via TDWD pin) monitors ST input transitions and asserts WDS on timeout-only active when at least one RST output is inactive.

Internal biasing ensures operation as long as either IN2.5V or IN3.3V exceeds 1.0V; accurate monitoring requires ≥1.5V on at least one supply input. All outputs are open-drain and require external pull-ups; internal 100kΩ pull-ups exist on PBRST2.5V, PBRST3.3V, and MPBRST pins.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Inputs	IN2.5V (1.0V–5.5V) and IN3.3V (1.0V–5.5V); device powers itself from the higher voltage
Reset Trip Points	IN2.5V: 2.000–2.375V (configurable via TOL2.5V); IN3.3V: 2.47–3.15V (configurable via TOL3.3V)
Reset Delay Options	10ms (TD = GND), 100ms (TD = float), 1000ms (TD = VCC) per supply
Watchdog Timeout	10ms/100ms/1000ms min (set by TDWD pin state)
Operating Temp	-40°C to +85°C - validated for industrial-grade thermal stability
Package	16-pin SOIC (150mil width), tape-and-reel (T&R) packaging for automated assembly
Output Type	Open-drain RST2.5V, RST3.3V, WDS, NMI1 - compatible with 3.3V/5V logic buses via external pull-up

Pinout & Package

DS1831DS+T&R is housed in a 16-pin SOIC (150mil body width, 1.27mm pitch), RoHS-compliant, surface-mount package optimized for high-density PCB layouts and reflow soldering.

Pin/Terminal	Circuit Role	Design Meaning
1 IN3.3V	3.3V supply input	Primary power source; used for internal bias and trip reference; must exceed 1.0V for operation
2 RST3.3V	3.3V reset output	Open-drain active-low signal asserting during out-of-tolerance or power-up/down events
3 TOL3.3V	Tolerance select for IN3.3V	GND = 10%, IN3.3V = 5%, float = 20% - sets trip threshold at power-up only
4 TD3.3V	Time-delay select for RST3.3V	GND = 10ms, float = 100ms, VCC = 1000ms - defines minimum active-reset duration
5 PBST	Pushbutton status output	Open-drain indicator of last reset origin (DS1831E only); not present on DS1831DS+T&R - pin 5 is NC
6 NMI1	Non-maskable interrupt 1	Open-drain output triggered when IN1 falls below 1.25V ±50mV; includes 100µV hysteresis
7 WDS	Watchdog status output	Open-drain active-low pulse (≥100µs) on watchdog timeout; requires external pull-up
8 TDWD	Watchdog time-delay select	GND = 10ms, float = 100ms, VCC = 1000ms - configures watchdog timeout period
9 IN2.5V	2.5V supply input	Secondary power source; internal operation uses higher of IN2.5V or IN3.3V
10 RST2.5V	2.5V reset output	Open-drain active-low signal synchronized to IN2.5V validity and TD2.5V setting
11 TOL2.5V	Tolerance select for IN2.5V	GND = 10%, IN2.5V = 5%, float = 15% - sets trip point at power-on
12 TD2.5V	Time-delay select for RST2.5V	GND = 10ms, float = 100ms, VCC = 1000ms - defines hold time after recovery
13 PBRST2.5V	2.5V pushbutton reset input	Pulled up internally to IN2.5V (100kΩ); low pulse ≥20µs triggers manual reset
14 IN1	Voltage sense input 1	Monitors external rail via resistor divider; referenced to 1.25V internal bandgap
15 ST	Watchdog strobe input	Edge-sensitive (any transition); resets watchdog timer; must be strobed within timeout window
16 GND	Ground reference	Common return for all analog and digital functions; decoupling capacitor required near pin

Key Features

Feature	Design Value
Dual-supply monitoring	Simultaneous supervision of 2.5V and 3.3V rails with independent trip thresholds and delays
Configurable watchdog timer	Three timeout options (10ms/100ms/1s) set by TDWD pin; prevents software lockup in microcontroller systems
Open-drain NMI outputs	NMI1 provides fault-triggered interrupt for upstream supplies; 100µV hysteresis rejects noise-induced false triggers
User-selectable tolerances	5%/10%/15% (IN2.5V) and 5%/10%/20% (IN3.3V) via TOL pin states - no external components needed
Flexible reset timing	Independent TD2.5V/TD3.3V pins allow asymmetric reset hold times for sequenced power-up

Applications

Industrial PLC Power Sequencing	Telecom Line Card Supervision
Use Scenario: A programmable logic controller powers multiple I/O modules requiring strict sequencing of 2.5V FPGA core and 3.3V interface rails. IC Role / Device Role / Timing Role: DS1831DS+T&R monitors both rails, asserts RST2.5V and RST3.3V with independently configured delays (100ms and 10ms) to ensure FPGA configuration completes before peripheral initialization. Use Value: Eliminates need for discrete RC timers and dual supervisor ICs; reduces BOM count and layout area while guaranteeing deterministic power-up order.	Use Scenario: A line card in an optical transport system must detect brownouts on its 3.3V data-path supply and 2.5V clock-synthesis supply. IC Role / Device Role / Timing Role: DS1831DS+T&R supervises both supplies using 5% tolerance on IN3.3V and 10% on IN2.5V, triggering RST3.3V first to halt data transmission before clock failure propagates. Use Value: Prevents packet corruption during partial power loss; configurable tolerances match actual supply regulation specs without overdesign.
Embedded Network Router	Medical Diagnostic Imaging Module
Use Scenario: A multi-core ARM-based router runs Linux and requires watchdog supervision alongside dual-voltage reset control. IC Role / Device Role / Timing Role: DS1831DS+T&R's ST input connects to a GPIO toggled by the OS watchdog daemon; WDS ties to PBRST3.3V to force full-system reset on software hang. Use Value: Integrates voltage monitoring and watchdog into single IC - avoids separate MAX6361 + MAX6371 solution, saving board space and interconnect complexity.	Use Scenario: An MRI subsystem uses isolated DC-DC converters feeding 2.5V ADC front-end and 3.3V FPGA control logic, requiring fail-safe shutdown on any rail collapse. IC Role / Device Role / Timing Role: DS1831DS+T&R monitors both rails and feeds RST2.5V/RST3.3V to FPGA's global reset; NMI1 watches isolated 12V bias supply via resistor divider. Use Value: Single-chip solution meets IEC 62304 Class C safety requirements for redundant voltage fault detection and controlled shutdown sequence.

Industrial PLC Power Sequencing

Telecom Line Card Supervision

Use Scenario: A programmable logic controller powers multiple I/O modules requiring strict sequencing of 2.5V FPGA core and 3.3V interface rails.

IC Role / Device Role / Timing Role: DS1831DS+T&R monitors both rails, asserts RST2.5V and RST3.3V with independently configured delays (100ms and 10ms) to ensure FPGA configuration completes before peripheral initialization.

Use Value: Eliminates need for discrete RC timers and dual supervisor ICs; reduces BOM count and layout area while guaranteeing deterministic power-up order.

Use Scenario: A line card in an optical transport system must detect brownouts on its 3.3V data-path supply and 2.5V clock-synthesis supply.

IC Role / Device Role / Timing Role: DS1831DS+T&R supervises both supplies using 5% tolerance on IN3.3V and 10% on IN2.5V, triggering RST3.3V first to halt data transmission before clock failure propagates.

Use Value: Prevents packet corruption during partial power loss; configurable tolerances match actual supply regulation specs without overdesign.

Embedded Network Router

Medical Diagnostic Imaging Module

Use Scenario: A multi-core ARM-based router runs Linux and requires watchdog supervision alongside dual-voltage reset control.

IC Role / Device Role / Timing Role: DS1831DS+T&R's ST input connects to a GPIO toggled by the OS watchdog daemon; WDS ties to PBRST3.3V to force full-system reset on software hang.

Use Value: Integrates voltage monitoring and watchdog into single IC - avoids separate MAX6361 + MAX6371 solution, saving board space and interconnect complexity.

Use Scenario: An MRI subsystem uses isolated DC-DC converters feeding 2.5V ADC front-end and 3.3V FPGA control logic, requiring fail-safe shutdown on any rail collapse.

IC Role / Device Role / Timing Role: DS1831DS+T&R monitors both rails and feeds RST2.5V/RST3.3V to FPGA's global reset; NMI1 watches isolated 12V bias supply via resistor divider.

Use Value: Single-chip solution meets IEC 62304 Class C safety requirements for redundant voltage fault detection and controlled shutdown sequence.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multisupply monitoring applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX6361ESA+	Single 3.3V supervisor only; no 2.5V monitoring, no watchdog, no NMI inputs	Suitable only for single-rail systems; lacks sequencing capability	Select when only basic 3.3V reset is required and cost is primary constraint
TPS3808G33DBVR	Single 3.3V supervisor with adjustable delay; no dual-supply support, no watchdog, no sense inputs	Designed for simple microprocessor reset; cannot monitor secondary rails or external voltages	Choose for low-power, single-supply applications where footprint and quiescent current are critical

Compared with MAX6361ESA+ and TPS3808G33DBVR, DS1831DS+T&R uniquely integrates dual-supply supervision, watchdog timer, and NMI-capable sense inputs in one 16-pin SOIC - enabling compact, feature-rich power management without stacking discrete supervisors.

Availability

DS1831DS+T&R is available at Aetrix Electronics and suitable for industrial automation, telecom infrastructure, and medical electronics requiring stable component supply, long-term lifecycle assurance, and tape-and-reel delivery for SMT production.

Supply support for DS1831DS+T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for power management, sensing, and communication applications.

The DS1831DS+T&R belongs to the MicroMonitor™ family, engineered specifically for robust, multi-rail voltage supervision in mission-critical embedded systems with watchdog safety enforcement.

FAQ

What is the function of the TDWD pin on the DS1831DS+T&R?

The TDWD pin on the DS1831DS+T&R selects the watchdog timeout period: grounded for 10ms, floating for 100ms, or tied to VCC for 1000ms minimum. This pin directly configures the ST-input watchdog timer that pulses WDS low if no edge occurs within the selected interval. The DS1831DS+T&R requires this pin to be externally biased for predictable watchdog behavior.

Can DS1831DS+T&R monitor voltages other than 2.5V and 3.3V?

Yes - DS1831DS+T&R includes two dedicated sense inputs (IN1 and ST) referenced to its internal 1.25V bandgap. Using external resistor dividers, users can monitor arbitrary voltages (e.g., 5V, 12V, or -5V) by scaling them down to 1.25V. The DS1831DS+T&R's NMI1 output activates when IN1 falls below 1.25V ±50mV, providing flexible upstream rail supervision beyond its primary supply inputs.

Does DS1831DS+T&R support independent reset timing for each supply rail?

Yes - DS1831DS+T&R provides fully independent reset timing control via TD2.5V and TD3.3V pins. Each accepts GND/float/VCC to set 10ms/100ms/1000ms minimum active-reset durations for RST2.5V and RST3.3V respectively. This enables precise power-up sequencing, such as holding the 2.5V FPGA core in reset for 100ms while releasing the 3.3V interface after 10ms - a capability confirmed in the DS1831DS+T&R datasheet timing tables.

What is the minimum supply voltage required for DS1831DS+T&R to operate?

The DS1831DS+T&R requires at least one of its supply inputs (IN2.5V or IN3.3V) to be ≥1.0V to maintain functional outputs; however, accurate voltage monitoring demands ≥1.5V on at least one supply input. Below 1.5V, the DS1831DS+T&R holds all reset outputs active but cannot reliably detect trip conditions - a design constraint explicitly defined in the Recommended DC Operating Conditions table.

How does the DS1831DS+T&R handle power-down events?

During power-down, DS1831DS+T&R asserts RST2.5V and RST3.3V when their respective supply inputs fall below the programmed trip thresholds. The reset remains active for up to 10µs after supply decay (tRPD parameter), ensuring clean system shutdown. As long as either IN2.5V or IN3.3V stays ≥1.0V, the DS1831DS+T&R sustains valid outputs - a key reliability feature for brownout resilience in industrial environments.

DS1831DS+T&R Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc./Maxim Integrated

Series:: MicroMonitor™

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Multi-Voltage Supervisor

Number of Voltages Monitored:: 4

Voltage - Threshold:: 2.5V, 3.3V, Adj

Output:: Open Drain or Open Collector

Reset:: Active Low

Reset Timeout:: 10ms; 100ms; 1,000ms Minimum

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

DS1831DS+T&R FAQ

1.How can I place an order for DS1831DS+T&R through Aetrix?

Please submit a Request for Quotation (RFQ) for DS1831DS+T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for DS1831DS+T&R reliable?

The price and inventory of DS1831DS+T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1831DS+T&R is usually 5 days.

3.What payment methods are accepted for DS1831DS+T&R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1831DS+T&R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for DS1831DS+T&R?

DS1831DS+T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your DS1831DS+T&R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for DS1831DS+T&R?

For technical support, including DS1831DS+T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1831DS+T&R requirements.

6.How does Aetrix verify that DS1831DS+T&R is sourced from the original manufacturer or authorized distributors?

All DS1831DS+T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1831DS+T&R meets industry standards.

7.What is the process for return or replacement of DS1831DS+T&R?

All DS1831DS+T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1831DS+T&R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The DS1831DS+T&R part is unused and in its original packaging.

Return procedure for DS1831DS+T&R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…