Analog Devices Inc./Maxim Integrated DS1867E-010/T&R
- Part No.:
- DS1867E-010/T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Digital Potentiometers
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS1867E-010/T&R.pdf
- Description:
- IC DGT POT 10KOHM 256TAP 20TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1867E-010/T&R from Maxim Integrated (now Analog Devices) is a dual-channel, nonvolatile digital potentiometer with EEPROM wiper storage, 10 kΩ end-to-end resistance per channel, 256-position resolution, and 3-wire serial interface. It operates from a single 5V supply, maintains wiper settings during power loss, and supports stacked configuration for 512-step combined resolution in precision analog gain/attenuation circuits.
For engineers reviewing the DS1867E-010/T&R datasheet, DS1867E-010/T&R pinout, DS1867E-010/T&R application, or DS1867E-010/T&R equivalent, this page delivers verified electrical specs, SOIC-16 package mapping, wiper nonvolatility behavior, cascade daisy-chaining capability, and real-world use cases in programmable amplifier and attenuator designs.
Technical Context
The DS1867E-010/T&R implements two independent 256-tap resistive dividers controlled via a 3-wire serial port (RST, CLK, DQ), with internal 17-bit shift register storing wiper positions and stack-select bit. Wiper values are retained in EEPROM shadow memory during power-down, triggered automatically when VCC drops below 4.5 V.
It supports stacked operation (H0–W0–SOUT and H1–W1–SOUT) to double total resistance while preserving 256-step resolution per pot, and cascading via COUT→DQ daisy chain for multi-device control on one bus - both functions confirmed in device block diagram and timing diagrams.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resistance Value | 10 kΩ per potentiometer - sets gain/attenuation range in op-amp feedback networks without external scaling. |
| Wiper Resolution | 256 positions (8-bit) - enables fine-grained analog tuning with ~39 Ω step size (10 kΩ / 256). |
| Nonvolatility | EEPROM-based wiper storage - retains last setting across power cycles; >25,000 write endurance. |
| Supply Voltage | 4.5 V to 5.5 V - compatible with standard 5 V logic rails; no ±5 V bias required for DS1867E-010/T&R variant. |
| Operating Temp | -40°C to +85°C - qualified for industrial environments including motor control and sensor signal conditioning. |
| Interface Speed | DC to 10 MHz CLK - supports fast reconfiguration in closed-loop calibration systems. |
| Wiper Resistance | 400 Ω to 1000 Ω - impacts accuracy in high-impedance nodes; minimized by using wiper as virtual ground reference. |
Pinout & Package
DS1867E-010/T&R is supplied in 16-pin SOIC (300-mil) package. Pin 1 = VB (substrate bias), Pin 16 = VCC, Pin 7 = GND, Pin 8 = DQ, Pin 9 = COUT, Pin 10 = LO, Pin 11 = HO, Pin 12 = WO, Pin 13 = SOUT, Pin 14 = H1, Pin 15 = NC, Pin 16 = VCC. Pins 2 and 15 are No Connect (NC); VB must be tied to GND for 5 V single-supply operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VB | Substrate bias | Must be connected to GND for 5 V operation; enables proper MOSFET channel control in resistor array. |
| VCC | +5 V supply input | Primary power rail; powers EEPROM write circuitry and digital logic; trip point at 4.5 V initiates auto-store. |
| GND | Ground reference | Common return for analog resistors and digital interface; critical for linearity and noise immunity. |
| RST | Serial port reset | Active-high enable; must transition low→high to initiate communication; low state latches wiper update. |
| CLK | Serial clock input | Synchronizes 17-bit shift register load; rising edge captures DQ data; max 10 MHz rate. |
| DQ | Data I/O | Serial bidirectional data line; carries wiper values and stack-select bit; requires pull-up for read mode. |
| COUT | Cascade output | Drives DQ of next device in daisy chain; 70 ns propagation delay enables reliable multi-device timing. |
| H0, H1 | High-end terminals | Fixed resistor endpoints; connect to supply or op-amp output depending on gain/attenuator topology. |
| L0, L1 | Low-end terminals | Fixed resistor endpoints; typically grounded or connected to reference voltage in variable-gain amps. |
| W0, W1 | Wiper outputs | Analog taps; used individually or multiplexed via SOUT in stacked mode; wiper resistance affects loading. |
| SOUT | Stacked wiper output | Multiplexed output of W0 or W1 based on stack-select bit; used when potentiometers are series-connected. |
Key Features
| Feature | Design Value |
|---|---|
| Nonvolatile wiper storage | EEPROM shadow memory retains last position across power cycles without external backup power or supercapacitors. |
| Stacked configuration support | Two 10 kΩ pots in series yield 20 kΩ total resistance with 512 effective steps - doubles range without sacrificing resolution. |
| Cascadable 3-wire interface | Single microcontroller GPIOs control multiple DS1867E-010/T&R units via daisy-chained COUT→DQ routing. |
| Low-power operation | 250 µA typical supply current at 5 V enables use in battery-backed or energy-constrained industrial modules. |
| Industrial temperature rating | Guaranteed performance from -40°C to +85°C supports deployment in PLC I/O modules and outdoor sensor interfaces. |
Applications
| Programmable Gain Amplifier | Digitally Tuned Attenuator |
|---|---|
|
Use Scenario: Op-amp circuit where closed-loop gain must be adjusted dynamically via MCU during system calibration or mode switching. IC Role / Device Role / Timing Role: Dual potentiometer provides feedback and input impedance ratio control; wiper positions updated over 3-wire serial interface. Use Value: Enables precise, repeatable gain settings (e.g., Av = –n/(255–n)) without mechanical trimmers or DAC+resistor networks. |
Use Scenario: RF or audio signal path requiring calibrated attenuation levels selected by firmware, not manual adjustment. IC Role / Device Role / Timing Role: Acts as digitally controlled voltage divider; H0/L0 forms fixed-ratio divider while W0 feeds downstream stage. Use Value: Delivers stable 10 kΩ impedance with ±0.75 LSB absolute linearity - critical for consistent signal level matching. |
| Multi-Channel Sensor Calibration | Industrial Current Loop Interface |
|
Use Scenario: Factory calibration of 4–20 mA transmitter modules where offset and span must be trimmed per unit. IC Role / Device Role / Timing Role: One pot sets zero-point offset, the other adjusts full-scale span; both stored nonvolatily after calibration. Use Value: Eliminates need for laser-trimmed resistors or EEPROM + external DAC, reducing BOM count and test time. |
Use Scenario: Isolated 4–20 mA loop driver where loop compliance voltage and sense resistor ratio require field-adjustable tuning. IC Role / Device Role / Timing Role: Configures feedback network of current-sense op-amp and output transistor; wipers set via isolated UART-to-serial bridge. Use Value: Supports remote firmware updates to loop parameters without hardware change - essential for predictive maintenance systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual digital potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5232BRUZ10 | 2.7–5.5 V supply; SPI interface; 1024-step resolution; on-chip EEPROM; 14-lead TSSOP. | Higher resolution and wider voltage range, but no native cascade support; requires separate CS lines per device. | Choose AD5232BRUZ10 for higher precision in low-voltage systems where SPI is preferred and daisy chaining is unnecessary. |
| MCP42010-I/P | 2.7–5.5 V supply; SPI interface; 256-step resolution; volatile wiper (no EEPROM); 14-pin PDIP/SOIC. | Lacks nonvolatility - wiper resets on power cycle; requires host MCU to reload settings at startup. | Choose MCP42010-I/P only if cost sensitivity outweighs need for persistent settings and system boot-time latency is acceptable. |
Compared with DS1867E-010/T&R, AD5232BRUZ10 offers finer resolution and broader supply range but lacks built-in cascade capability, while MCP42010-I/P eliminates EEPROM overhead at the cost of requiring full initialization on every power-up - making DS1867E-010/T&R optimal for unattended industrial nodes needing guaranteed post-power-on behavior.
Availability
DS1867E-010/T&R is available at Aetrix Electronics and suitable for programmable gain amplifiers, digitally tuned attenuators, multi-channel sensor calibration, and industrial current loop interfaces requiring stable component supply and long-term parametric consistency.
Supply support for DS1867E-010/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (formerly Maxim Integrated) designs high-performance analog, mixed-signal, and RF ICs for precision measurement, industrial automation, and communications infrastructure.
The DS1867E-010/T&R belongs to Maxim's legacy digital potentiometer family, engineered specifically for replacing mechanical trimmers in industrial control, sensor conditioning, and calibration-critical analog signal paths.
FAQ
What is the resistance tolerance and temperature coefficient of the DS1867E-010/T&R?
The DS1867E-010/T&R has ±20% end-to-end resistance tolerance at 25°C and a temperature coefficient of 750 ppm/°C. These values are specified in the Analog Resistor Characteristics table and directly impact gain stability in temperature-varying environments - for example, a 10 kΩ channel may drift up to ±7.5 Ω/°C, requiring compensation in high-accuracy applications.
Does the DS1867E-010/T&R require external components for EEPROM write operation?
No, the DS1867E-010/T&R performs automatic EEPROM wiper storage during power-down without external capacitors or circuitry. When VCC falls below 4.5 V, the device detects the drop and initiates an internal write sequence - provided the power-down time from 4.5 V to 3.0 V exceeds 4 ms, as defined in the Power-Down EEPROM Timing Requirements.
Can the DS1867E-010/T&R operate from a single 3.3 V supply?
No, the DS1867E-010/T&R is specified only for 4.5 V to 5.5 V operation per its Recommended DC Operating Conditions. Attempting 3.3 V operation violates the minimum VCC requirement and will prevent reliable EEPROM writes, serial communication, and wiper positioning - use AD5232 or MAX5487 for true 3.3 V-compatible alternatives.
How does the stacked configuration affect linearity in the DS1867E-010/T&R?
In stacked mode, the DS1867E-010/T&R maintains ±0.75 LSB absolute linearity and ±0.30 LSB relative linearity per potentiometer - identical to standalone operation. The SOUT output selects either W0 or W1 via the stack-select bit, so linearity remains unchanged; total resistance becomes 20 kΩ, but step resolution stays at ~39 Ω per tap.
What is the maximum number of DS1867E-010/T&R devices that can be cascaded reliably?
The DS1867E-010/T&R datasheet confirms daisy-chain operation but does not specify a hard upper limit. Practical constraints include cumulative propagation delay (70 ns per device), clock skew, and signal integrity on long COUT→DQ traces. For robust operation at 10 MHz CLK, ≤8 devices are recommended; beyond that, reduce clock frequency or add series termination resistors.
DS1867E-010/T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 256
- Resistance (Ohms):
- 10k
- Interface:
- Serial
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 5V
- Features:
- Cascade Pin
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 750ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-TSSOP
- Operating Temperature:
- -40°C ~ 85°C
- Resistance - Wiper (Ohms) (Typ):
- 400
DS1867E-010/T&R FAQ
1.How can I place an order for DS1867E-010/T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1867E-010/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1867E-010/T&R reliable?
The price and inventory of DS1867E-010/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1867E-010/T&R is usually 5 days.
3.What payment methods are accepted for DS1867E-010/T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1867E-010/T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1867E-010/T&R?
DS1867E-010/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1867E-010/T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1867E-010/T&R?
For technical support, including DS1867E-010/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1867E-010/T&R requirements.
6.How does Aetrix verify that DS1867E-010/T&R is sourced from the original manufacturer or authorized distributors?
All DS1867E-010/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1867E-010/T&R meets industry standards.
7.What is the process for return or replacement of DS1867E-010/T&R?
All DS1867E-010/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS1867E-010/T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1867E-010/T&R part is unused and in its original packaging.
Return procedure for DS1867E-010/T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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