Analog Devices Inc./Maxim Integrated DS1867E-10
- Part No.:
- DS1867E-10
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Digital Potentiometers
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS1867E-10.pdf
- Description:
- IC DGT POT 10KOHM 256TAP 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,712
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1867E-10 from Maxim Integrated (now Analog Devices) is a dual-channel, nonvolatile digital potentiometer with EEPROM wiper storage, 10 kΩ end-to-end resistance per channel, 256-position resolution, and 3-wire serial interface. It operates from a single 5V supply and maintains wiper settings across power cycles for precision analog trimming in industrial sensor conditioning and programmable gain amplifiers.
For engineers reviewing the DS1867E-10 datasheet, DS1867E-10 pinout, DS1867E-10 application, or DS1867E-10 equivalent, key selection considerations include EEPROM endurance (25,000 writes), stacked configuration support (512-step combined resolution), ±0.75 LSB absolute linearity, and cascading capability for multi-device bus control.
Technical Context
The DS1867E-10 implements two independent 256-tap resistor ladders with EEPROM-backed shadow memory that auto-saves wiper positions during power-down when VCC drops below 4.5 V. Its 3-wire serial port (RST/CLK/DQ) uses an active-high RST to enable communication and latches 17-bit data on CLK rising edges - including stack-select bit and both 8-bit wiper values.
It supports stacked operation via SOUT multiplexing (selecting W0 or W1 based on bit-0 of the shift register) and daisy-chain cascading through COUT→DQ propagation (70 ns max delay). The device requires no charge pump, enabling quiet, low-power operation (250–900 µA ICC) while maintaining full analog signal integrity across -40°C to +85°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resistance Value | 10 kΩ per potentiometer; sets maximum analog range and gain scaling in amplifier/attenuator circuits. |
| Wiper Resolution | 256 positions (8-bit); enables fine-grained adjustment with ~39 Ω step size per tap at 10 kΩ. |
| Nonvolatility | EEPROM shadow memory retains wiper settings without power; auto-saves during VCC drop below 4.5 V with ≥4 ms power-down time. |
| Linearity | ±0.75 LSB absolute linearity; ensures ≤0.3% voltage error vs ideal ladder output across full travel. |
| Serial Interface | 3-wire (RST/CLK/DQ); supports daisy-chaining multiple devices with COUT-to-DQ feedback for read/write over shared bus. |
| Operating Temp | -40°C to +85°C industrial grade; validated for embedded systems in harsh environments without derating. |
| Wiper Resistance | 400–1000 Ω; impacts loading error in high-impedance nodes; minimized by using wiper with op-amp inputs. |
Pinout & Package
DS1867E-10 is packaged in a 16-pin SOIC (300-mil) surface-mount package with exposed pad not connected. Pin functions are electrically validated per Maxim's DS1867 datasheet Rev 102199.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VB | Substrate bias input | Must be tied to GND for standard 5V operation; enables bipolar resistor voltage swing if biased at -5V. |
| VCC | Positive supply | Single 4.5–5.5 V rail powers logic and analog ladders; internal regulation ensures stable reference. |
| GND | Ground reference | Common return for supply, logic, and resistor terminals; critical for noise immunity in analog paths. |
| RST | Serial port enable | Active-high signal initiating all communication; must transition low after each 17-bit transaction to commit wiper update. |
| CLK | Serial clock input | Drives synchronous data latching on rising edge; supports up to 10 MHz for fast reconfiguration. |
| DQ | Serial bidirectional data | Carries 17-bit I/O shift register contents (stack bit + W1 + W0); requires external pull-up for open-drain compatibility. |
| COUT | Cascade output | Drives DQ of next device in daisy chain; 70 ns propagation enables reliable multi-device timing. |
| SOUT | Stacked wiper output | Multiplexes W0 or W1 based on stack-select bit; used for series-connected 20 kΩ total resistance with 512-step resolution. |
| H0/H1 | Potentiometer high ends | Connect to positive voltage rails or signal sources; define upper voltage boundary of each ladder. |
| L0/L1 | Potentiometer low ends | Connect to GND or negative references; define lower voltage boundary; must not go below VB. |
| W0/W1 | Individual wiper outputs | Provide variable voltage taps; wiper resistance (400–1000 Ω) requires buffering for low-impedance loads. |
Key Features
| Feature | Design Value |
|---|---|
| Pumpless 5V operation | Eliminates switching noise and EMI from charge pumps, preserving signal integrity in sensitive analog front-ends. |
| Auto-store EEPROM | Guarantees wiper retention without software intervention-critical for fail-safe calibration in unattended systems. |
| Stacked configuration | Enables 20 kΩ total resistance with same 256-step resolution per pot, doubling effective travel without hardware change. |
| Cascadable serial bus | Reduces MCU GPIO count and PCB routing complexity when managing multiple DS1867E-10 units in one system. |
| Industrial temperature range | Validated performance from -40°C to +85°C ensures reliability in factory automation, outdoor instrumentation, and motor controls. |
Applications
| Programmable Gain Amplifier | Calibration-Enabled Sensor Interface |
|---|---|
Use Scenario: Inverting amplifier where DS1867E-10 adjusts feedback resistance to set gain from -1× to -255× dynamically. IC Role / Device Role / Timing Role: Dual-potentiometer provides digitally controlled, nonvolatile gain scaling; wiper position defines Av = -n/(255−n). Use Value: Enables field-upgradable gain without recalibration; 10 kΩ value matches common op-amp stability requirements. | Use Scenario: Offset and span trimming for pressure transducers in industrial PLC modules operating across wide temperature ranges. IC Role / Device Role / Timing Role: Nonvolatile wiper stores calibrated zero and full-scale points; retains settings through power cycling and thermal drift. Use Value: Eliminates manual potentiometers and reduces calibration labor; ±0.75 LSB linearity ensures <0.3% measurement error. |
| Fixed-Gain Signal Attenuator | Multi-Channel Bias Control |
Use Scenario: Precision attenuation of audio or sensor signals before ADC sampling, with fixed attenuation ratio selected at startup. IC Role / Device Role / Timing Role: One potentiometer acts as voltage divider; second remains unused or configured for redundancy. Use Value: 10 kΩ resistance minimizes loading on source; wiper resistance variation (400–1000 Ω) is negligible when driving high-Z op-amp inputs. | Use Scenario: Independent DC bias setting for four-channel analog front-end in medical EEG acquisition system. IC Role / Device Role / Timing Role: Two DS1867E-10 units cascade via COUT/DQ to configure eight independent bias voltages from one microcontroller. Use Value: Reduces component count versus discrete DACs; EEPROM storage preserves patient-specific calibration profiles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual digital potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5232BRUZ10 | 2.7–5.5 V supply; SPI interface; 1024-step resolution; internal EEPROM with 50k write endurance. | Higher resolution and wider supply range, but lacks SOUT stacking and cascading COUT functionality. | Choose AD5232BRUZ10 for higher precision and SPI-native MCU integration; avoid if stacked resistance or daisy-chain control is required. |
| MCP42010-I/P | 5V-only; SPI interface; volatile wiper (no EEPROM); 256-step; includes shutdown mode and TCON register. | No nonvolatility; requires external memory or firmware restore on power-up; no stacking or cascading support. | Choose MCP42010-I/P for cost-sensitive, short-cycle applications where wiper persistence is managed externally. |
Compared with AD5232BRUZ10 and MCP42010-I/P, the DS1867E-10 uniquely combines EEPROM-based nonvolatility, hardware-supported stacking (SOUT), and native daisy-chain capability (COUT) in a single 5V 3-wire interface-making it optimal for distributed analog trimming where reliability and bus efficiency are critical.
Availability
DS1867E-10 is available at Aetrix Electronics and suitable for industrial sensor calibration, programmable gain amplifiers, and multi-channel bias control requiring stable component supply, long-term obsolescence management, and guaranteed traceable sourcing.
Supply support for DS1867E-10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Maxim Integrated in 2021) designs high-performance analog, mixed-signal, and RF ICs for precision measurement, industrial automation, and communications infrastructure.
The DS1867E-10 belongs to Maxim's legacy digital potentiometer family engineered for nonvolatile, low-noise analog trimming in embedded systems where EEPROM-backed calibration persistence is mandatory.
FAQ
What is the supply voltage range for the DS1867E-10?
The DS1867E-10 operates from a single 4.5 V to 5.5 V supply (VCC). It does not support ±5 V operation in this variant - that capability applies only to the DS1867 base part without the "E" suffix. The DS1867E-10 is optimized for 5 V systems and includes internal regulation to maintain stable analog ladder performance across the specified range.
Does the DS1867E-10 require external components for EEPROM write functionality?
No, the DS1867E-10 performs automatic EEPROM writes without external components. When VCC drops below 4.5 V, the device detects the power-down condition and initiates an internal auto-store sequence - provided the voltage remains between 4.5 V and 3.0 V for at least 4 ms. This guarantees wiper position retention without firmware intervention or external circuitry.
Can the DS1867E-10 be used in stacked configuration to achieve 20 kΩ total resistance?
Yes, the DS1867E-10 supports hardware stacking: connecting H1 to L0 forms a 20 kΩ series ladder, and the SOUT pin delivers the combined wiper output. The stack-select bit (bit-0 of the 17-bit shift register) determines whether SOUT reflects W0 or W1. This yields 512 effective steps while preserving 10 kΩ per segment's 256-step resolution and linearity.
What is the maximum clock frequency supported by the DS1867E-10 serial interface?
The DS1867E-10 supports a maximum CLK frequency of 10 MHz, with minimum pulse width of 50 ns. Timing parameters including data setup (30 ns), hold (10 ns), and propagation delay (70 ns) are fully characterized across -40°C to +85°C. This allows rapid reconfiguration - e.g., updating both wipers in under 1.7 µs - making the DS1867E-10 suitable for real-time gain adjustment loops.
How many write cycles can the EEPROM in the DS1867E-10 endure?
The EEPROM in the DS1867E-10 is rated for a minimum of 25,000 write cycles under standard conditions (-40°C to +85°C, VCC = 5 V ±10%). Each write corresponds to a full power-down event that triggers auto-store. If wiper values remain unchanged during power cycles, EEPROM wear is avoided - extending functional life well beyond 25,000 cycles in typical calibration applications.
DS1867E-10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 256
- Resistance (Ohms):
- 10k
- Interface:
- Serial
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 5V
- Features:
- Cascade Pin
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 750ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-TSSOP
- Operating Temperature:
- -40°C ~ 85°C
- Resistance - Wiper (Ohms) (Typ):
- 400
DS1867E-10 FAQ
1.How can I place an order for DS1867E-10 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1867E-10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1867E-10 reliable?
The price and inventory of DS1867E-10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1867E-10 is usually 5 days.
3.What payment methods are accepted for DS1867E-10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1867E-10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1867E-10?
DS1867E-10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1867E-10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1867E-10?
For technical support, including DS1867E-10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1867E-10 requirements.
6.How does Aetrix verify that DS1867E-10 is sourced from the original manufacturer or authorized distributors?
All DS1867E-10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1867E-10 meets industry standards.
7.What is the process for return or replacement of DS1867E-10?
All DS1867E-10 units undergo pre-shipment inspection (PSI). If there is an issue with DS1867E-10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1867E-10 part is unused and in its original packaging.
Return procedure for DS1867E-10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1867E-10 Tags

-
MCP4018T-103E/LT
Microchip Technology

-
MCP4018T-503E/LT
Microchip Technology

-
MCP4011T-103E/SN
Microchip Technology

-
MCP4018T-104E/LT
Microchip Technology

-
MCP4017T-503E/LT
Microchip Technology

-
MCP4018T-502E/LT
Microchip Technology

-
MCP4017T-103E/LT
Microchip Technology

-
MCP4531T-103E/MF
Microchip Technology

-
MCP4021T-202E/SN
Microchip Technology

-
MCP4023T-103E/CH
Microchip Technology

-
MCP4022T-503E/CH
Microchip Technology

-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

