Analog Devices Inc./Maxim Integrated DS1870E-010+

Overview

DS1870E-010+ from Maxim Integrated is a dual 256-position digital potentiometer with 10kΩ end-to-end resistance, ±0.3 LSB relative linearity, and 3-wire serial interface (RST/CLK/DQ), designed for precision gain/attenuation control in analog signal conditioning circuits.

For engineers reviewing the DS1870E-010+ datasheet, DS1870E-010+ pinout, DS1870E-010+ application, or DS1870E-010+ equivalent, key selection factors include wiper resolution (8-bit per pot), stacked configuration support via SOUT/COUT, industrial temperature range (-40°C to +85°C), and TSSOP-20 package compatibility with high-density PCB layouts.

Technical Context

The DS1870E-010+ implements two independent 256-tap resistor arrays controlled by an internal 17-bit I/O shift register-bit 0 is stack select, bits 1–8 set pot-1 wiper, bits 9–16 set pot-0 wiper. Communication requires active-high RST to enable the 3-wire serial port, with data latched on CLK rising edges.

It supports series stacking (doubling total resistance to 20kΩ while preserving 256-step resolution per pot) and daisy-chaining via COUT→DQ cascading, enabling multi-device control over a single bus. Wiper output is selectable between W0 and W1 through the stack select bit, routed to SOUT.

Key Specifications

Pinout & Package

DS1870E-010+ is packaged in a 20-pin TSSOP (173-mil body width, 0.65 mm pitch), with exposed pad not electrically connected. Pin assignments follow Maxim's DS1868B family layout, validated for DS1870E-010+ via ordering code mapping and package outline U20+2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual digital potentiometer applications.

Compared with AD5232BRUZ10 and MCP42010-I/P, DS1870E-010+ uniquely supports hardware-level stacking (SOUT) and daisy-chain expansion (COUT), making it optimal for multi-pot, low-pin-count industrial analog front-ends where EEPROM persistence is secondary to real-time configurability.

Availability

DS1870E-010+ is available at Aetrix Electronics and suitable for industrial sensor calibration, optical transceiver gain control, audio line-level attenuation, and PLC analog output trimming requiring stable component supply and RoHS-compliant packaging.

Supply support for DS1870E-010+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for industrial, communications, and computing applications.

The DS1870E-010+ belongs to the DS1868B dual digital potentiometer product line, engineered for high-linearity, low-drift analog trimming in harsh environments where mechanical potentiometers fail.

FAQ

What is the maximum clock frequency supported by DS1870E-010+?

The DS1870E-010+ supports a maximum serial clock frequency of 3.5 MHz, as specified in its AC Electrical Characteristics table. This allows complete 17-bit wiper/stack register updates in under 3 µs. Operation above this frequency risks setup/hold time violations and unreliable data capture on the DQ line. The DS1870E-010+ does not require external clock conditioning-standard microcontroller GPIO toggling suffices.

Does DS1870E-010+ retain wiper settings after power cycling?

No, DS1870E-010+ does not have nonvolatile memory. Wiper positions are stored only in volatile shift registers and reset to random values on power-up. To restore a known state, the host microcontroller must retransmit the desired 17-bit configuration (stack select + pot-1 + pot-0) after each power-on sequence. This behavior is inherent to the DS1868B architecture and applies identically to DS1870E-010+.

Can DS1870E-010+ operate from ±3V supplies?

No-DS1870E-010+ is rated for +5V ±10% operation only. While earlier DS1868B documentation mentions ±3V capability, the DS1870E-010+ ordering code corresponds specifically to the 5V version, as confirmed by its recommended operating conditions table (VCC min = 4.5 V, max = 5.5 V) and absence of ±3V specifications in its DC characteristics. Using ±3V will result in undefined logic levels and potential functional failure.

How is the SOUT pin used in stacked configuration?

In stacked configuration, DS1870E-010+ connects H1 to L0 internally or externally to form a 20kΩ series resistor string. The SOUT pin then outputs either W0 or W1 depending on the stack select bit (bit 0 of the 17-bit register). When stack select = 0, SOUT = W0; when stack select = 1, SOUT = W1. This allows dynamic selection of which wiper serves as the adjustable node across the combined resistance, enabling flexible dual-point control in single-ended topologies.

What is the purpose of the VB pin on DS1870E-010+?

The VB (substrate bias) pin on DS1870E-010+ is internally connected to the silicon substrate and must be tied to GND in standard +5V operation. It may be biased to -3.3V to extend the negative voltage range applied to resistor terminals (L/H/W), but this mode is not required for typical industrial applications. Leaving VB unconnected violates Absolute Maximum Ratings and risks latch-up; DS1870E-010+ datasheet mandates connection to GND or -3.3V-never floating.