Analog Devices Inc./Maxim Integrated DS21372T+

Overview

DS21372T+ from Maxim Integrated (now Analog Devices) is a 3.3V software-programmable Bit Error Rate Tester (BERT) IC for digital communications test equipment. It integrates pattern generation (pseudorandom up to 2³²−1, repetitive up to 32 bits), error detection (BER up to 10⁻²), and 32-bit error/bit counters. It operates from DC to 20 MHz and supports CCITT/ITU O.151–O.161 standards in T1, Fractional-T1, Smart Jack, and CSU/DSU validation.

For engineers reviewing the DS21372T+ datasheet, DS21372T+ pinout, DS21372T+ application, or DS21372T+ equivalent, this device delivers full transmit/receive independence, programmable error insertion (10⁻¹ to 10⁻⁷), Intel/Motorola bus compatibility via BTS pin, and real-time RLOS/SYNC status reporting - critical for loopback automation and BER measurement in telecom infrastructure test systems.

Technical Context

The DS21372T+ implements dual independent data paths: a programmable LFSR-based pseudorandom pattern generator with configurable polynomial taps (PTR) and length (PLR), and a synchronous pattern detector that validates received data against the transmitted sequence using auto-resync logic. Its 32-bit error and bit counters are latched on LC/PCR.4 assertion and cleared automatically, enabling precise integration-period control.

It features an 8-bit multiplexed parallel interface with selectable Intel/Motorola timing (BTS pin), hardware interrupt (INT) driven by status events (SYNC, BED, BECOF), and dedicated control pins (TL, RL, LC, TDIS, RDIS) for deterministic pattern loading, receive capture, and clock-gated operation - essential for gap-clocking applications like Fractional-T1 and switched-56 kbps testing.

Key Specifications

Pinout & Package

DS21372T+ is housed in a 32-pin Thin Quad Flat Package (TQFP) with 0.8 mm pitch, dimensions 7.0 mm × 7.0 mm body size, 1.0 mm max height (A2), and 0.45–0.75 mm lead length (L). Pin 1 is top-left corner, marked by dot or bevel.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar bit error rate testing applications.

Compared with DS21372T+, DS2141A+ offers lower cost but sacrifices 20 MHz bandwidth, programmable error injection, and ITU O.161 compliance; MAX3675 targets gigabit serial links and lacks the parallel bus, pattern flexibility, and telecom-specific features essential for T1/E1 test instrumentation.

Availability

DS21372T+ is available at Aetrix Electronics and suitable for T1/E1 line testing, CSU/DSU validation, Smart Jack diagnostics, and router/bridge link verification requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for DS21372T+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices (acquired Maxim Integrated in 2021) designs precision analog, mixed-signal, and digital ICs for instrumentation, communications, and industrial systems.

The DS21372T+ belongs to Maxim's telecom test IC product line, engineered specifically for bit-level validation of digital transmission facilities including T1, E1, and fractional services - emphasizing programmability, wide frequency range, and standards compliance.

FAQ

What is the maximum operating frequency of the DS21372T+?

The DS21372T+ operates from DC to 20 MHz on both transmit (TCLK) and receive (RCLK) clocks. This supports full-rate testing of T1 (1.544 MHz), E1 (2.048 MHz), and higher-rate digital links within its specification, with timing validated down to 50 ns clock period (20 MHz) per AC characteristics.

Does the DS21372T+ support both pseudorandom and user-defined test patterns?

Yes, the DS21372T+ supports two distinct pattern modes: pseudorandom sequences (e.g., 2²³−1, 2³²−1 per ITU O.151–O.153) via programmable polynomial length and tap registers, and user-defined repetitive patterns of 1–32 bits loaded into the Pattern Set Registers - enabling both standards-compliant and custom diagnostic sequences.

How does the DS21372T+ handle bit error rate calculation?

The DS21372T+ provides 32-bit Bit Count Register (BCR) and Bit Error Count Register (BECR) values. BER is calculated externally as BECR / BCR. The LC pin or PCR.4 bit latches these counts and resets internal accumulators, allowing precise definition of the measurement integration window for repeatable, traceable results.

Can the DS21372T+ operate with both Intel and Motorola microprocessor buses?

Yes, the DS21372T+ features a configurable parallel interface. The BTS pin selects timing mode: low for Intel (ALE/WR/RD), high for Motorola (AS/DS/RW). Address/data multiplexing and timing parameters (e.g., tCYC = 200 ns) are fully specified for both configurations in the datasheet.

What is the purpose of the RLOS and SYNC signals in the DS21372T+?

RLOS (Pin 23) is an active-high output indicating loss of receive synchronization; SYNC (bit SR.0) is a real-time status flag in the Status Register. Together, they provide immediate hardware visibility into pattern lock state - enabling automated resync, test abort, or pass/fail decisions without continuous register polling.