Analog Devices Inc./Maxim Integrated DS2165QL

Overview

DS2165QL from Maxim Integrated (now Analog Devices) is a 3V-compatible ADPCM voice compression/expansion processor IC optimized for TDM-based telephony systems. It performs real-time 64kbps ↔ 32/24/16kbps adaptive-differential PCM conversion per channel, supports dual independent channels (X/Y), operates on a 10MHz master clock, and delivers sub-375µs input-to-output latency. It is used in voice storage, digital PBX, and channel-bundled telecom interface designs.

For engineers reviewing the DS2165QL datasheet, DS2165QL pinout, DS2165QL application, or DS2165QL equivalent, key selection considerations include its 3V supply operation (2.7–3.6V), hardware-mode configurability without host processor, on-the-fly algorithm switching between G.721, T1.303, and proprietary 16kbps modes, and direct interconnection with combo-codec devices such as TP305x and MC1455xx series.

Technical Context

The DS2165QL implements a dual-channel, time-slot programmable ADPCM engine with independent control registers for X and Y sides. Each channel supports selectable A-law/µ-law coding, bypass/idle modes, and algorithm reset-configured via either serial port (software mode) or address pins (hardware mode). Its TSAC circuit enables flexible time-slot assignment for PCM/ADPCM I/O across TDM frames.

It requires asynchronous 10MHz MCLK for DSP core timing while accepting frame-synced PCM clocks (CLKX/CLKY, FSX/FSY) at standard rates (1.544MHz or 2.048MHz). Input-to-output delay remains under 375µs regardless of selected compression rate (32/24/16kbps) or time-slot configuration, and CAS signaling is supported via automatic 32↔24kbps algorithm switching upon double-wide frame sync detection.

Key Specifications

Pinout & Package

DS2165QL is housed in a 28-pin Plastic Leaded Chip Carrier (PLCC) package with 0.050" pitch, dimensions per JEDEC MS-026 (D2 = 0.390–0.430", E2 = 0.390–0.430"). Pin 14 is VSS (signal ground); pin 28 is VDD (3.0V supply); pin 13 is MCLK (10MHz input); pins 16–18 and 27–25 serve X-side and Y-side PCM interfaces respectively.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ADPCM processor applications.

Compared with DS2165Q and TLV320AIC23B, the DS2165QL uniquely combines 3V operation, sub-375µs latency, hardware-mode configurability, and CAS-aware algorithm switching-making it the only drop-in solution for space-constrained, low-power telecom voice processing where G.721/T1.303 compliance and TDM time-slot precision are required.

Availability

DS2165QL is available at Aetrix Electronics and suitable for voice storage systems, digital PBX interfaces, telecom gateway voice cards, and codec interfacing modules requiring stable component supply across extended production lifecycles.

Supply support for DS2165QL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (acquired by Analog Devices in 2021) is a semiconductor company specializing in high-performance analog, mixed-signal, and RF solutions for industrial, communications, and computing markets.

The DS2165QL belongs to Maxim's legacy telecom DSP processor family, designed specifically for voiceband compression in TDM-based infrastructure-emphasizing low-latency, multi-algorithm flexibility, and minimal host dependency.

FAQ

What voltage range does the DS2165QL support, and how does it differ from the DS2165Q?

The DS2165QL operates from 2.7V to 3.6V, making it compatible with modern 3V logic systems and reducing power consumption to 12mA typical. In contrast, the DS2165Q requires 4.5V to 5.5V and draws 20mA typical. This difference means DS2165QL can be used directly in battery-backed or mixed-voltage telecom modules without level shifters, whereas DS2165Q mandates a dedicated 5V rail. Both share identical pinout, register mapping, and functional capabilities.

Does the DS2165QL support Channel Associated Signaling (CAS), and how is it implemented?

Yes, the DS2165QL supports CAS through automatic 32kbps ↔ 24kbps algorithm switching triggered by a double-wide frame sync pulse on FSX or FSY. When configured for G.721 (32kbps), the device detects this extended sync and transitions to T1.303 (24kbps) mode-freeing the LSB of the ADPCM output for signaling bits. This occurs autonomously without host processor involvement, preserving real-time behavior and simplifying CAS implementation in digital loop carrier or R2 signaling systems.

Can the DS2165QL perform compression and expansion simultaneously on its two channels?

Yes, the DS2165QL's dual fully independent channel architecture allows one channel (e.g., X) to compress 64kbps PCM to 24kbps while the other (Y) expands incoming 16kbps ADPCM back to 64kbps-within the same device and clock domain. Each channel has its own control register, time-slot assignment, data format (A-law/µ-law), and algorithm selection, enabling true concurrent bidirectional voice processing essential for echo-cancelling conferencing systems or hybrid voice/data gateways.

What is the purpose of the SPS pin on the DS2165QL, and what happens when it is tied low?

The SPS (Serial Port Select) pin determines configuration mode: when tied high, DS2165QL enters software mode and accepts serial commands via SCLK/SDI/CS; when tied low, it enters hardware mode-disabling the serial port and repurposing A0–A5, SDI, and CS as direct control inputs for algorithm, coding, and idle state. In hardware mode, no external host is needed, time slots default to 0, and power consumption drops significantly during idle-ideal for standalone voice recorders or fixed-function telecom peripherals.

How does the DS2165QL handle time-slot assignment for PCM and ADPCM data streams?

The DS2165QL uses on-board time-slot assigner-circuit (TSAC) logic to independently program input and output time slots for each channel via dedicated 6-bit registers. Time slot size (4-bit vs. 8-bit) depends on CP/EX setting: compression yields 4-bit ADPCM slots; expansion yields 8-bit PCM slots. For example, with CP/EX = 1 (compress) and µ-law input, XIN accepts 32 × 8-bit slots while XOUT outputs 64 × 4-bit slots-all configurable without changing frame sync frequency or requiring external timing logic.