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Texas Instruments DS25CP104TSQX/NOPB
- Part No.:
- DS25CP104TSQX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
DS25CP104TSQX/NOPB.pdf
- Description:
- IC CROSSPOINT SW 1 X 4:4 40WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,374
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Product details
Overview
DS25CP104TSQX/NOPB from Texas Instruments (formerly National Semiconductor) is a 3.125 Gbps 4×4 LVDS crosspoint switch with integrated transmit pre-emphasis (Off/Low/Medium/High) and receive equalization (Off/Low/Medium/High), designed for high-speed signal routing across lossy FR-4 backplanes and balanced cables in SDI routers and Fibre Channel systems. It features fully differential non-blocking architecture, on-chip 100 Ω input/output termination, and dual configuration modes (pin-strapped or SMBus).
For engineers reviewing the DS25CP104TSQX/NOPB datasheet, DS25CP104TSQX/NOPB pinout, DS25CP104TSQX/NOPB application, or DS25CP104TSQX/NOPB equivalent, key selection considerations include its 4-level programmable PE/EQ capability, 8 kV HBM ESD rating on LVDS I/O, flow-through LLP-40 package layout, and support for both broadcast (1:4) and quad-buffer (4:4) switching modes.
Technical Context
The DS25CP104TSQX/NOPB implements a fully differential, non-blocking 4×4 LVDS switch fabric with independent per-output pre-emphasis and per-input equalization control. Its dual-mode operation-pin-configurable (EN_smb = 0) or SMBus-programmable (EN_smb = 1)-enables flexible system integration: pin mode supports two-level PE/EQ (Off/Medium and Off/Low), while SMBus mode enables full four-level control plus loss-of-signal (LOS) monitoring and soft power-down.
Internally terminated 100 Ω differential inputs and outputs minimize insertion loss and eliminate external termination components. The device accepts LVDS, CML, and LVPECL input levels (0.05 V to VCC−0.05 V common-mode range) and delivers compliant LVDS outputs (250–450 mV differential voltage, 1.05–1.375 V offset).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Architecture | 4×4 non-blocking LVDS crosspoint with independent input-to-output routing |
| Max Data Rate | 3.125 Gbps per channel - supports 3G-SDI, OC-48, and 2G Fibre Channel |
| Pre-emphasis Levels | 4 levels (Off/Low/Medium/High) via SMBus; 2 levels (Off/Medium) via pins - compensates channel loss up to 9.7 dB at 1.56 GHz |
| Equalization Levels | 4 levels (Off/Low/Medium/High) via SMBus; 2 levels (Off/Low) via pins - recovers signals degraded by inter-symbol interference |
| Differential Skew | ≤125 ps channel-to-channel skew - ensures timing alignment across all 4 outputs in broadcast mode |
| ESD Rating | 8 kV HBM on LVDS I/O - protects against handling-induced discharge without external protection |
| Supply Voltage | 3.0 V to 3.6 V - compatible with standard 3.3 V logic rails and tolerant of ±10% variation |
| Operating Temp | −40°C to +85°C - qualified for industrial and broadcast equipment environments |
Pinout & Package
The DS25CP104TSQX/NOPB uses a 40-pin LLP (Leadless Leadframe Package) measuring 6 mm × 6 mm with exposed thermal pad (DAP), optimized for high-density PCB layouts and thermal dissipation. Its flow-through pinout minimizes trace crossovers and preserves signal integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0+ / IN0− to IN3+ / IN3− (Pins 1,2,4,5,6,7,9,10) | Differential LVDS Inputs | Accept LVDS/CML/LVPECL signals; internally terminated 100 Ω; support wide common-mode range (0.05 V to VCC−0.05 V) |
| OUT0+ / OUT0− to OUT3+ / OUT3− (Pins 21–24,26–29) | Differential LVDS Outputs | Deliver 250–450 mV LVDS swing; 100 Ω internal termination; low skew (≤125 ps) |
| EQ0–EQ3 (Pins 11,12,39,40) | LVCMOS Equalization Select | Set per-input EQ level (Off/Low in pin mode; all 4 levels via SMBus); functional regardless of EN_smb state |
| PE0–PE3 (Pins 18–20,31) | LVCMOS Pre-emphasis Select | Set per-output PE level (Off/Medium in pin mode; all 4 levels via SMBus); functional regardless of EN_smb state |
| EN_smb (Pin 17) | SMBus Enable Input | Pull-down enabled; logic high activates SMBus mode (SCL/SDA on S00/S01); resets SMBus registers on toggle |
| PWDN (Pin 38) | Power-Down Control | Active-low; powers down core circuitry while retaining SMBus/LOS functionality when EN_smb = 1 |
| S00/SCL & S01/SDA (Pins 36,37) | Configurable I/O | In pin mode: input select for OUT0; in SMBus mode: clock/data interface - eliminates need for dedicated SMBus pins |
| VDD (Pins 3,8,15,25,30) & GND (Pins 16,DAP) | Power & Ground | Five VDD pins and dual ground (pin + DAP) reduce supply noise and improve thermal performance |
Key Features
| Feature | Design Value |
|---|---|
| On-chip 100 Ω differential termination | Eliminates 8 external resistors per channel, reduces BOM count, and cuts board area by ≥30% vs discrete termination |
| Programmable pre-emphasis & equalization | Four independent PE levels per output and EQ levels per input enable precise channel loss compensation across varying cable/backplane lengths |
| Loss-of-signal (LOS) monitoring | Detects open-cable faults on any input and reports status via SMBus register (Address 0x04), enabling system-level link health diagnostics |
| SmartPWDN power management | Automatically powers down unused I/O blocks and logic based on active routing configuration - reduces ICC by up to 40% in partial-use scenarios |
| Flow-through LLP-40 package | 6 mm × 6 mm footprint with input-to-output signal path alignment simplifies PCB routing and maintains controlled impedance |
| 8 kV HBM ESD protection | Protects LVDS I/O pins during handling and system integration without requiring external TVS diodes |
Applications
| SD/HD/3G-SDI Routers | OC-48 / STM-16 Optical Transport |
|---|---|
Use Scenario: Routing multiple uncompressed HD/3G video streams between processing modules and output interfaces in broadcast production switchers. IC Role / Device Role / Timing Role: 4×4 LVDS crosspoint switch providing low-jitter (<0.16 UIP-P at 3.125 Gbps), skew-controlled signal distribution with adaptive equalization to compensate for long PCB traces. Use Value: Enables single-device routing of four independent 3G-SDI channels (2.97 Gbps) with deterministic jitter margin >20% over SMPTE 424M spec. | Use Scenario: Interfacing SONET framer ICs to optical line cards in telecom central office equipment operating at OC-48 line rate (2.488 Gbps). IC Role / Device Role / Timing Role: High-speed signal conditioner and multiplexer that equalizes degraded framer outputs and routes them to redundant transmitters. Use Value: Compensates up to 9.7 dB channel loss at 1.56 GHz (per test channel F), extending reach over FR-4 backplanes without external redrivers. |
| Fibre Channel (2GFC) | InfiniBand DDR (2.5 Gbps) |
Use Scenario: Switching between dual-port FC HBAs and storage controllers in enterprise server blade chassis with midplane interconnects. IC Role / Device Role / Timing Role: Non-blocking 4×4 LVDS switch supporting 2.125 Gbps Fibre Channel links with configurable pre-emphasis to drive 20-inch FR-4 traces. Use Value: Reduces bit error rate (BER) by >10× vs un-equalized paths using Medium EQ + Medium PE settings per validated test channel B. | Use Scenario: Aggregating InfiniBand DDR links from compute nodes to a central switch fabric in HPC clusters using multi-drop backplane topologies. IC Role / Device Role / Timing Role: Low-skew (≤125 ps) crosspoint enabling simultaneous fanout of clock and data lanes to four destinations with matched propagation delay. Use Value: Maintains <100 ps eye width at 2.5 Gbps after 30-inch FR-4 channel (test channel E), meeting InfiniBand DDR electrical compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS crosspoint switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX9154ESE+ | 4×4 LVDS crosspoint with fixed 200 mV pre-emphasis only; no receive equalization; 28-pin SOIC package | Lacks adaptive EQ for lossy channels; limited to shorter interconnects (<10 inches FR-4); no SMBus control | Select when cost-sensitive designs require basic switching without channel conditioning and can accept larger SOIC footprint. |
| SN65LVCP404RGZR | Texas Instruments' pin-compatible successor with enhanced 4.25 Gbps data rate, lower 0.8 W typical power, and extended EQ/PE resolution | Supports 12G-SDI and CPRI; requires updated firmware for SMBus register mapping; same LLP-40 footprint | Choose for new designs targeting higher bandwidth or lower power; existing DS25CP104TSQX/NOPB layouts are mechanically compatible but require register validation. |
Compared with MAX9154ESE+, DS25CP104TSQX/NOPB adds full receive equalization and SMBus configurability for dynamic channel adaptation; compared with SN65LVCP404RGZR, it offers proven qualification for broadcast infrastructure but lacks support for 12G-SDI and has higher typical power draw (175 mA vs 120 mA at 3.125 Gbps).
Availability
DS25CP104TSQX/NOPB is available at Aetrix Electronics and suitable for SDI router development, OC-48 transport equipment, and Fibre Channel storage interconnects requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized channels.
Supply support for DS25CP104TSQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments acquired National Semiconductor in 2011 and maintains full technical and supply chain responsibility for legacy high-speed interface products including the DS25CP104 series.
The DS25CP104 belongs to TI's high-speed LVDS interface portfolio, engineered specifically for broadcast video, telecom transport, and storage systems where deterministic jitter, channel loss compensation, and compact packaging are critical design constraints.
FAQ
What is the maximum supported data rate for DS25CP104TSQX/NOPB?
The DS25CP104TSQX/NOPB is characterized and guaranteed to operate at up to 3.125 Gbps per channel under recommended conditions (VCC = 3.0–3.6 V, TA = −40°C to +85°C). Jitter performance metrics-including total jitter ≤0.16 UIP-P at 3.125 Gbps-are specified and tested per PRBS-23 NRZ patterns, confirming suitability for 3G-SDI and 2G Fibre Channel applications.
Does DS25CP104TSQX/NOPB support both pin-strapped and SMBus configuration modes?
Yes, DS25CP104TSQX/NOPB supports dual configuration modes. When EN_smb = 0, it operates in pin mode with two-level pre-emphasis (Off/Medium) and equalization (Off/Low). When EN_smb = 1, it enters SMBus mode, enabling full four-level PE/EQ control, loss-of-signal reporting, soft power-down, and user-defined slave addressing via ADDR0–ADDR3 pins.
How does the on-chip 100 Ω termination in DS25CP104TSQX/NOPB affect system design?
The DS25CP104TSQX/NOPB integrates 100 Ω differential termination on all eight LVDS I/O pairs (IN0–IN3, OUT0–OUT3), eliminating the need for eight external 100 Ω resistors. This reduces component count, saves ≥12 mm² board area, lowers insertion loss, and improves impedance matching-directly enhancing signal integrity on dense backplanes without additional layout complexity.
Can DS25CP104TSQX/NOPB accept CML or LVPECL inputs?
Yes, DS25CP104TSQX/NOPB accepts CML and LVPECL input levels due to its wide input common-mode range of 0.05 V to VCC−0.05 V (typical 1.2 V at 3.3 V supply). This allows direct interfacing with common high-speed drivers without level-shifting circuitry, provided differential input voltage remains within 0–1.0 V and peak-to-peak swing complies with LVDS receiver thresholds.
What is the purpose of the SmartPWDN feature in DS25CP104TSQX/NOPB?
SmartPWDN in DS25CP104TSQX/NOPB automatically powers down unused I/O blocks and supporting logic based on the active switch configuration-for example, disabling receivers for unselected inputs or transmitters for un-routed outputs. This reduces typical supply current by up to 40% in partial-use cases (e.g., 1:4 broadcast mode), improving thermal performance and system-level power efficiency without sacrificing configurability.
DS25CP104TSQX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Crosspoint Switch
- Circuit:
- 1 x 4:4
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-WQFN (6x6)
DS25CP104TSQX/NOPB FAQ
1.How can I place an order for DS25CP104TSQX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS25CP104TSQX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS25CP104TSQX/NOPB reliable?
The price and inventory of DS25CP104TSQX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS25CP104TSQX/NOPB is usually 5 days.
3.What payment methods are accepted for DS25CP104TSQX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS25CP104TSQX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS25CP104TSQX/NOPB?
DS25CP104TSQX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS25CP104TSQX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS25CP104TSQX/NOPB?
For technical support, including DS25CP104TSQX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS25CP104TSQX/NOPB requirements.
6.How does Aetrix verify that DS25CP104TSQX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS25CP104TSQX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS25CP104TSQX/NOPB meets industry standards.
7.What is the process for return or replacement of DS25CP104TSQX/NOPB?
All DS25CP104TSQX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS25CP104TSQX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS25CP104TSQX/NOPB part is unused and in its original packaging.
Return procedure for DS25CP104TSQX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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