Texas Instruments DS25CP114TSQ/NOPB
- Part No.:
- DS25CP114TSQ/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
DS25CP114TSQ/NOPB.pdf
- Description:
- IC CROSSPOINT SW 1 X 4:4 40WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS25CP114TSQ/NOPB from Texas Instruments is a 3.125 Gbps, 4×4 LVDS crosspoint switch optimized for high-speed signal routing over lossy FR-4 backplanes and balanced cables. It features fully differential non-blocking architecture, SMBus- and pin-configurable transmit pre-emphasis (4 levels) and receive equalization (4 levels), and eliminates on-chip 100 Ω input termination to enable custom multidrop topologies in SD/HD/3G-SDI routers and InfiniBand interconnects.
For engineers reviewing the DS25CP114TSQ/NOPB datasheet, DS25CP114TSQ/NOPB pinout, DS25CP114TSQ/NOPB application, or DS25CP114TSQ/NOPB equivalent, key selection criteria include its 3.125 Gbps data rate, absence of internal input termination, 4-level EQ/PE programmability via SMBus, and support for LVDS/CML/LVPECL input compatibility with LVDS outputs - all critical for high-fidelity serial video and telecom switching designs.
Technical Context
The DS25CP114TSQ/NOPB implements a fully differential, non-blocking 4×4 LVDS crosspoint matrix with independent input-to-output path routing. Its architecture supports both pin-strapped configuration (EN_smb = 0) and full SMBus register control (EN_smb = 1), enabling dynamic reconfiguration without hardware changes.
Unlike the DS25CP104A, the DS25CP114TSQ/NOPB omits internal 100 Ω differential input terminations - requiring external termination - while retaining internal 100 Ω output terminations. This design choice enables flexible multidrop signaling topologies and reduces capacitive loading on source drivers in broadcast or fanout applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | DC to 3.125 Gbps - supports 3G-SDI, OC-48, and InfiniBand signaling without retiming. |
| Input Termination | No internal 100 Ω input termination - requires external termination for impedance matching and signal integrity control. |
| Output Termination | Integrated 100 Ω differential output termination - minimizes return loss and simplifies PCB layout. |
| Pre-emphasis Levels | 4 configurable levels (Off/Low/Medium/High) via SMBus - compensates for channel loss up to 9.7 dB at 1.56 GHz. |
| Equalization Levels | 4 configurable levels (Off/Low/Medium/High) via SMBus - recovers degraded eye openings from lossy FR-4 traces. |
| Jitter Performance | Total jitter ≤ 0.16 UIP–P at 3.125 Gbps (PRBS-23) with EQ=High/PE=High - meets SDI and telecom timing budgets. |
| Supply Voltage | 3.0 V to 3.6 V - compatible with standard 3.3 V logic rails and low-noise power domains. |
Pinout & Package
DS25CP114TSQ/NOPB is housed in a 40-pin WQFN package (6 mm × 6 mm, 0.5 mm pitch) with exposed thermal pad (DAP) requiring connection to GND for optimal electrical and thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0+ / IN0− to IN3+ / IN3− | LVDS Input Pairs | Differential high-speed inputs; no internal termination - external 100 Ω must be placed at source or receiver per topology. |
| OUT0+ / OUT0− to OUT3+ / OUT3− | LVDS Output Pairs | Differential outputs with integrated 100 Ω termination - drives standard 100 Ω differential loads directly. |
| EQ0–EQ3 | LVCMOS Equalization Control | Selects EQ level (Off/Low/Medium/High) per input pair; functional in both pin and SMBus modes. |
| PE0–PE3 | LVCMOS Pre-emphasis Control | Selects PE level (Off/Low/Medium/High) per output pair; functional in both pin and SMBus modes. |
| S00/SCL, S01/SDA, S10–S21/ADDR0–ADDR3, S30/S31 | Mode-Dependent I/O | In Pin Mode: input select pins (Sxx); in SMBus Mode: clock/data/address pins (SCL/SDA/ADDRn) - dual-function interface. |
| PWDN | Power-Down Control | Active-low enable; powers down core circuitry while preserving SMBus accessibility when EN_smb = 1. |
| EN_smb | SMBus Enable | LVCMOS input with internal 20 kΩ pulldown; high = SMBus mode, low = pin-strapped mode. |
| VDD / GND / DAP | Power & Ground | Five VDD pins distributed for low-impedance supply; DAP must be soldered to GND plane for thermal/electrical stability. |
Key Features
| Feature | Design Value |
|---|---|
| Eliminated input termination | Enables custom multidrop topologies and avoids fixed 100 Ω loading - critical for fanout and daisy-chain routing. |
| 4-level adaptive EQ + PE | Compensates for up to 9.7 dB channel loss at 1.56 GHz; allows dynamic tuning per link without hardware change. |
| Loss-of-signal (LOS) monitoring | Detects open-input fault conditions (e.g., disconnected cable) and reports status via SMBus registers - improves system diagnostics. |
| 8 kV HBM ESD protection | Protects LVDS I/O pins against electrostatic discharge during handling and board integration - reduces field failure risk. |
| Flow-through pinout | Minimizes trace length and layer transitions; supports straight-through routing on dense high-speed PCBs. |
Applications
| SD/HD/3G-SDI Routers | OC-48 / STM-16 Line Cards |
|---|---|
|
Use Scenario: Routing uncompressed HD/3G-SDI video streams across redundant backplane paths in broadcast infrastructure. IC Role / Device Role / Timing Role: 4×4 LVDS crosspoint switch providing non-blocking, low-jitter signal path selection with adaptive equalization to restore degraded video eye diagrams. Use Value: Enables reliable 3G-SDI (2.97 Gbps) distribution over 20-inch FR-4 traces without external redrivers - reducing BOM count and board area. |
Use Scenario: Signal multiplexing and path switching in SONET OC-48 line interface cards operating at 2.488 Gbps. IC Role / Device Role / Timing Role: High-speed LVDS crosspoint managing bidirectional OC-48 data lanes between framer, PHY, and backplane connectors. Use Value: Maintains <0.16 UIP–P total jitter at 2.5 Gbps with EQ=Medium/PE=Low - meeting GR-253-CORE jitter compliance for telecom equipment. |
| InfiniBand Switch Fabric | FireWire 800 Backplane Interconnect |
|
Use Scenario: Building scalable 4×4 switching nodes in InfiniBand QDR (40 Gbps aggregate) fabric cards. IC Role / Device Role / Timing Role: Low-skew (≤125 ps channel-to-channel), low-jitter crosspoint enabling deterministic latency routing of 10 Gbps per lane signals. Use Value: Supports broadcast (1:4) and unicast (1:1) modes with <650 ps propagation delay - preserves InfiniBand sub-microsecond latency requirements. |
Use Scenario: High-bandwidth FireWire 800 (786 Mbps) interconnect between host controllers and peripheral expansion modules. IC Role / Device Role / Timing Role: LVDS signal router adapting legacy FireWire physical layer to modern FPGA-based host interfaces with CML/LVPECL compatibility. Use Value: Wide input common-mode range (0.05 V to VCC − 0.05 V) allows direct interfacing to FireWire PHYs without level-shifting components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 4×4 LVDS crosspoint switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS25CP104ATSQ/NOPB | Includes internal 100 Ω input termination; otherwise identical pinout, speed, and EQ/PE capability. | Better suited for point-to-point links where fixed input termination simplifies layout; not suitable for multidrop topologies. | Select DS25CP104ATSQ/NOPB when using single-ended source drivers or when minimizing external component count is prioritized over topology flexibility. |
| MAX9154ESE+ | 3.2 Gbps max rate; no SMBus interface; only pin-strapped configuration; no pre-emphasis or equalization. | Limited to static routing in lower-loss channels; lacks adaptive signal conditioning for long FR-4 traces or cables. | Select MAX9154ESE+ only for cost-sensitive, fixed-configuration applications with short (<10") interconnects and no jitter-critical timing. |
Compared with DS25CP104ATSQ/NOPB, DS25CP114TSQ/NOPB trades built-in input termination for multidrop design freedom; compared with MAX9154ESE+, it adds full adaptive EQ/PE and SMBus configurability - making it uniquely suitable for high-reliability, field-upgradable serial video and telecom switching systems.
Availability
DS25CP114TSQ/NOPB is available at Aetrix Electronics and suitable for SD/HD/3G-SDI routers, OC-48 line cards, and InfiniBand switch fabric applications requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.
Supply support for DS25CP114TSQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions, with decades of expertise in signal integrity and high-frequency design.
The DS25CP114TSQ/NOPB belongs to TI's high-speed LVDS crosspoint switch product line, engineered specifically for lossy-backplane signal routing in broadcast video, telecom transport, and high-performance computing interconnects.
FAQ
What is the key functional difference between DS25CP114TSQ/NOPB and DS25CP104ATSQ/NOPB?
The DS25CP114TSQ/NOPB omits internal 100 Ω differential input termination, requiring external termination for each input pair, whereas the DS25CP104ATSQ/NOPB integrates 100 Ω input termination on all four LVDS inputs. This makes DS25CP114TSQ/NOPB ideal for multidrop or custom-terminated topologies, while DS25CP104ATSQ/NOPB suits simpler point-to-point links. Both share identical pinout, 3.125 Gbps performance, SMBus/EQ/PE capability, and WQFN-40 packaging.
Does DS25CP114TSQ/NOPB support LVPECL or CML inputs?
Yes, DS25CP114TSQ/NOPB supports LVPECL and CML inputs due to its wide input common-mode voltage range (0.05 V to VCC − 0.05 V) and differential input voltage tolerance up to VCC + 0.6 V. This allows direct interfacing with common high-speed driver families without level-shifting circuitry - confirmed in the device's DC Electrical Characteristics table under "LVDS INPUT DC SPECIFICATIONS".
How is SMBus address configured on DS25CP114TSQ/NOPB?
The DS25CP114TSQ/NOPB uses a 7-bit SMBus slave address with hardwired MSBs "101" and user-configurable LSBs ADDR3–ADDR0 (pins S11, S21, S20, S10). Each ADDR pin is tied to VCC (logic 1) or GND (logic 0) to set the 4-bit address field, enabling up to 16 devices on one SMBus segment. Address configuration is active only when EN_smb = 1 (SMBus mode).
What is the purpose of the DAP (die attach pad) on DS25CP114TSQ/NOPB?
The DAP on DS25CP114TSQ/NOPB is an exposed thermal pad located beneath the WQFN package. It must be soldered directly to a solid GND plane on the PCB to ensure optimal thermal dissipation and electrical stability. TI specifies that failure to connect the DAP to GND degrades both junction temperature performance and signal integrity - particularly critical under sustained 3.125 Gbps operation.
Can DS25CP114TSQ/NOPB operate in both pin-strapped and SMBus modes simultaneously?
No, DS25CP114TSQ/NOPB operates exclusively in one mode at a time, determined by the logic level on EN_smb: low (0) enables Pin Mode (external pin configuration), and high (1) enables SMBus Mode (register-based control). The two modes are mutually exclusive; mixing configurations (e.g., SMBus writes while EN_smb = 0) has no effect, and pin functions like S00/S01 revert to input select roles when EN_smb = 0.
DS25CP114TSQ/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Crosspoint Switch
- Circuit:
- 1 x 4:4
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-WQFN (6x6)
DS25CP114TSQ/NOPB FAQ
1.How can I place an order for DS25CP114TSQ/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS25CP114TSQ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS25CP114TSQ/NOPB reliable?
The price and inventory of DS25CP114TSQ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS25CP114TSQ/NOPB is usually 5 days.
3.What payment methods are accepted for DS25CP114TSQ/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS25CP114TSQ/NOPB transactions.
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4.How is shipping managed for DS25CP114TSQ/NOPB?
DS25CP114TSQ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS25CP114TSQ/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS25CP114TSQ/NOPB?
For technical support, including DS25CP114TSQ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS25CP114TSQ/NOPB requirements.
6.How does Aetrix verify that DS25CP114TSQ/NOPB is sourced from the original manufacturer or authorized distributors?
All DS25CP114TSQ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS25CP114TSQ/NOPB meets industry standards.
7.What is the process for return or replacement of DS25CP114TSQ/NOPB?
All DS25CP114TSQ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS25CP114TSQ/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS25CP114TSQ/NOPB part is unused and in its original packaging.
Return procedure for DS25CP114TSQ/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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