Analog Devices Inc./Maxim Integrated DS3134

Overview

DS3134 from Maxim Integrated (formerly Dallas Semiconductor) is a 256-channel HDLC controller IC designed for high-density T1/E1 and T3/E3 line interface applications. It supports up to 64 T1/E1 data streams or two T3 lines, delivers 104 Mbps full-duplex throughput, features dual 52 Mbps fast HDLC engines on Ports 0 and 1, and integrates scatter/gather DMA with timestamped receive packets for telecom access equipment.

For engineers reviewing the DS3134 datasheet, DS3134 pinout, DS3134 application, or DS3134 equivalent, key selection criteria include channelized vs. unchannelized port configuration, per-channel DS0 loopback capability, V.54 pattern detection, onboard BERT assignment flexibility, and PCI Local Bus Specification v2.1 compliance at 32-bit/33 MHz.

Technical Context

The DS3134 implements a layered architecture with 16 physical ports-each configurable as channelized or unchannelized-and two dedicated fast HDLC engines (Ports 0 and 1, up to 52 Mbps), plus 14 standard HDLC engines (Ports 2–15, up to 10 Mbps). It supports ANSI T1.403-1995, ITU Q.921, and ISO 3309 for HDLC framing, CRC16/32, zero stuffing/destuffing, and abort handling.

Its DMA subsystem uses programmable descriptor bursting (8 or 16 descriptors), supports large/small buffer allocation up to 8191 bytes, and enables priority- or round-robin HDLC channel arbitration for FIFO-to-PCI transfers. The 16 kB transmit and 16 kB receive FIFOs use programmable low/high water marks and support time-stamped packet ingress and priority-tagged egress.

Key Specifications

Pinout & Package

DS3134 is housed in a 256-lead plastic ball grid array (BGA) package measuring 27 mm × 27 mm, optimized for high-speed serial interface routing and thermal dissipation in telecom line cards.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar HDLC controller applications.

Compared with DS3134, DS3133 offers half the channel density and no dual-fast-port capability-making it suitable only for mid-density access nodes-while PCI9054 provides no native HDLC functionality and shifts protocol handling entirely to external logic, increasing design complexity and component count.

Availability

DS3134 is available at Aetrix Electronics and suitable for telecom access nodes, xDSL line cards, T3/E3 aggregation systems, and military HSSI interfaces requiring stable component supply, long-lifecycle support, and traceable sourcing.

Supply support for DS3134 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (acquired by Analog Devices in 2021) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and digital communication ICs.

The DS3134 belongs to Maxim's Chateau family of channelized T1/E1 and HDLC controllers, engineered specifically for carrier-grade telecom infrastructure demanding high channel density, standards compliance, and integrated diagnostics.

FAQ

What is the maximum number of T1/E1 data streams supported by the DS3134?

The DS3134 supports up to 64 T1 or E1 data streams, as confirmed in the device description and revision history (Version 6 reinstated the 64-stream capability after a temporary revision downgrade). This capacity is achieved through flexible assignment of DS0 channels across its 16 physical ports, with each port configurable for one, two, or four T1/E1 lines in channelized mode. The DS3134 achieves this density using 256 independent HDLC channels and dual fast engines on Ports 0 and 1.

Does the DS3134 support both channelized and unchannelized operation on the same physical port?

Yes, the DS3134 allows each of its 16 physical ports to be independently configured as either channelized or unchannelized via the Layer One configuration registers (R[n]CFG[j]/T[n]CFG[j]). In channelized mode, Ports 0–15 handle T1/E1 framing with DS0-level granularity; in unchannelized mode, they operate as transparent bit pipes up to 10 Mbps (Ports 2–15) or 52 Mbps (Ports 0–1). The DS3134's architecture ensures no functional conflict between modes across ports.

How does the DS3134 implement Bit Error Rate Testing (BERT)?

DS3134 integrates a fully programmable BERT capable of generating and detecting pseudorandom (2^15–1, 2^23–1, 2^31–1) and repeating bit patterns on any selected HDLC channel or physical port. It includes auto-error insertion, 31-consecutive-bit detection (per Version 4 update), and counters that remain active during loss of receive synchronization. BERT control and status are accessed via dedicated registers (Section 5.6) and IEEE 1149.1 JTAG interface-no external test equipment is required for link validation.

What PCI specification versions and electrical characteristics does the DS3134 comply with?

The DS3134 complies with PCI Local Bus Specification v2.1 (June 1, 1995), operating as a 32-bit, 33 MHz target device. It supports burst transfers up to 256 dwords, uses 3.3 V signaling with 5 V tolerant I/O, and meets AC timing parameters defined in Section 12 of the datasheet-including tTRD, tRD, and tCO limits. The DS3134 does not support PCI-X or PCIe; its PCI interface is strictly v2.1-compliant for legacy telecom backplanes.

Can the DS3134 operate without external memory for descriptor management?

No-the DS3134 requires external system memory for DMA descriptor storage (Free Queue, Pending Queue, Done Queue), as all descriptors are hosted in the PCI-addressable memory space managed by the host CPU. The DS3134 contains no on-chip descriptor RAM; instead, it reads/writes descriptors directly from/to host memory using scatter/gather addressing. The DS3134 does include internal configuration RAM for HDLC, FIFO, and DMA control registers-but packet metadata always resides externally.